Inventor

STEMPEL BRIAN MICHAEL

US41 patents

⚠️ This page may combine multiple inventors who share the name “STEMPEL BRIAN MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STEMPEL BRIAN MICHAEL

QUALCOMM INC

Effective use of a BHT in processor having variable length instruction set execution modes

Link stack repair of erroneous speculative update

System, method and software to preload instructions from an instruction set other than one currently executing

System, method and software to preload instructions from a variable-length instruction set with proper pre-decoding

Power saving methods and apparatus to selectively enable cache bits based on known processor state

Pre-decode error handling via branch correction

Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions

Caching memory attribute indicators with cached memory data field

Apparatus for generating return address predictions for implicit and explicit subroutine calls

Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions

Method, apparatus, and system for memory bandwidth aware data prefetching

Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media

Cache memory error detection circuits for detecting bit flips in valid indicators in cache memory following invalidate operations, and related methods and processor-based systems

System and method for using a working global history register

Pre-decoding variable length instructions

Method and apparatus for prefetching non-sequential instruction addresses

Sliding-window, block-based branch target address cache

Caching instructions for a multiple-state processor

Handling cache miss in an instruction crossing a cache line boundary

Method and apparatus for managing cache partitioning using a dynamic boundary

Debug circuit comparing processor instruction set operating mode

Optimizing performance for context-dependent instructions

Methods and system for resolving simultaneous predicted branch instructions

Eliminating redundant masking operations instruction processing circuits, and related processor systems, methods, and computer-readable media

Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media

Dependency-prediction of instructions

Method to improve speed of executing return branch instructions in a processor

Fusing conditional write instructions having opposite conditions in instruction processing circuits, and related processor systems, methods, and computer-readable media

Method, apparatus, and system for prefetching exclusive cache coherence state for store instructions

Methods and apparatus for managing page crossing instructions with different cacheability

DIEFFENDERFER JAMES NORRIS

Link stack repair of erroneous speculative update

Link stack repair of erroneous speculative update

STEMPEL BRIAN MICHAEL

Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information

Selective powering of a BHT in a processor having variable length instructions

SMITH RODNEY WAYNE

Methods and system for resolving simultaneous predicted branch instructions

Predecode repair cache for instructions that cross an instruction cache line

KOTHARI KULIN N

Multi level indirect predictor using confidence counter and program counter address filter scheme

SARTORIUS THOMAS ANDREW

Preloading instructions from an instruction set other than a currently executing instruction set

MICROSOFT TECHNOLOGY LICENSING LLC

Operand-based reach explicit dataflow processors, and related methods and computer-readable media

STREETT DAREN EUGENE

Apparatus and methods for speculative interrupt vector prefetching

DEBRUYNE LESLIE MARK

Method and apparatus for tracking extra data permissions in an instruction cache