Inventor

BOUCHARD GREGG A

US62 patents

⚠️ This page may combine multiple inventors who share the name “BOUCHARD GREGG A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BOUCHARD GREGG A

CAVIUM INC

Work migration in a processor

System and method to provide non-coherent access to a coherent memory system

Packet extraction optimization in a network processor

Lookup cluster complex

Lookup front end packet input processor

Lookup cluster complex

System and method for rule matching in a processor

Method and apparatus for managing processing thread migration between clusters within a processor

System and method to reduce memory access latencies using selective replication across multiple memory ports

Engine architecture for processing finite automata

Lookup front end packet output processor

Phased bucket pre-fetch in a network processor

Content search mechanism that uses a deterministic finite automata (DFA) graph, a DFA state machine, and a walker process

Multi-host processing

Phased bucket pre-fetch in a network processor

Method and apparatus for scheduling rule matching in a processor

Method and an accumulator scoreboard for out-of-order rule response handling

HEWLETT PACKARD DEVELOPMENT CO

Computer architecture and system for efficient management of bi-directional bus

System for minimizing memory bank conflicts in a computer system

Mechanism to reorder memory read and write transactions for reduced latency and increased bandwidth

Computer resource management and allocation system

Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature

Mechanism to track all open pages in a DRAM memory system

GOYAL RAJAN

Work migration in a processor

Lookup front end packet input processor

Lookup cluster complex

Lookup front end packet output processor

Lookup front end packet input processor

Method and apparatus encoding a rule for a lookup request in a processor

CAVIUM NETWORKS INC

Selective replication of data structures

TCP engine

Packet queuing, scheduling and ordering

Direct access to low-latency memory

BOUCHARD GREGG A

On-chip memory (OCM) physical bank parallelism

Deterministic finite automata (DFA) processing

System and method for rule matching in a processor

Deterministic finite automata (DFA) instruction

ANSARI NAJEEB I

Method and apparatus for managing processing thread migration between clusters within a processor

Method and apparatus for assigning resources used to manage transport operations between clusters within a processor

Method and apparatus for managing transport operations to a cluster within a processor

Method and apparatus for managing transfer of transport operations from a cluster in a processor

CAVIUM NETWORKS

IPsec performance optimization

Random number generator

PANGBORN JEFFREY

System and method to reduce memory access latencies using selective replication across multiple memory ports

System and method to provide non-coherent access to a coherent memory system

PANGBORN JEFFREY A

Method and apparatus for multiple access of plural memory banks

AGERE SYSTEMS INC

Dynamic random access memory system with bank conflict avoidance feature

COMPAQ INFORMATION TECHNOLOGIE

Proprammable DRAM address mapping mechanism

HUSSAIN MUHAMMAD R

Content search mechanism that uses a deterministic finite automata (DFA) graph, a DFA state machine, and a walker process

CAVIUM LLC

Methods and apparatus for a unified baseband architecture