Inventor

HSU LOUIS C

US65 patents

⚠️ This page may combine multiple inventors who share the name “HSU LOUIS C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HSU LOUIS C

IBM

High performance FET with elevated source/drain region

CMOS well structure and method of forming the same

Interconnect structure and method for forming the same

Micro-cavity MEMS device and method of fabricating same

Simultaneous grain modulation for BEOL applications

Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application

Reprogrammable electrical fuse

MIM capacitor and method of fabricating same

Electrical programmable metal resistor

SOI field effect transistor with a back gate for modulating a floating body

Structure and method of fabricating a hinge type MEMS switch

Modified via bottom structure for reliability enhancement

Fuse/anti-fuse structure and methods of making and programming same

Interconnect structures with encasing cap and methods of making thereof

SOI CMOS compatible multiplanar capacitor

Integrated circuit chip with FETs having mixed body thickness and method of manufacture thereof

Fuse/anti-fuse structure and methods of making and programming same

Interconnect structures with encasing cap and methods of making thereof

Laser annealing for 3-D chip integration

Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof

High performance FET with elevated source/drain region

Microelectronic circuit structure with layered low dielectric constant regions and method of forming same

Circuit structure with low dielectric constant regions and method of forming same

Dielectric interconnect structures and methods for forming the same

On-chip electrically alterable resistor

Precision tuning of a phase-change resistive element

Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application

MIM capacitor and method of fabricating same

Microelectronic circuit structure with layered low dielectric constant regions

Structure and method for MOSFET gate electrode landing pad

High Speed Multi-Mode Receiver with adaptive receiver equalization and controllable transmitter pre-distortion

Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof

Body capacitor for SOI memory description

Avoiding device stressing

High-speed multi-mode receiver

Interconnect structures with encasing cap and methods of making thereof

Partial wafer bonding and dicing

SRAM device, and SRAM device design structure, with adaptable access transistors

Modified via bottom structure for reliability enhancement

CHEN HOWARD H

Sea-of-fins structure on a semiconductor substrate and method of fabrication

Sea-of-fins structure on a semiconductor substrate and method of fabrication

Apparatus for nonvolatile multi-programmable electronic fuse system

YANG CHIH-CHAO

Dielectric interconnect structures and methods for forming the same

Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application

Methods for forming dielectric interconnect structures

CLEVENGER LAWRENCE A

Circuit structure with low dielectric constant regions

Structure and method for MOSFET gate electrode landing pad

CHENG KANGGUO

FinFET fuse with enhanced current crowding

HSU LOUIS C

Reprogrammable electrical fuse

CHAN YUEN H

Dual beta ratio SRAM