Inventor
KIM SUNGRYUL
US49 patents
⚠️ This page may combine multiple inventors who share the name “KIM SUNGRYUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
QUALCOMM INC
32 patentsUS9455013B2Sep 27, 2016
System and method to trim reference levels in a resistive memory
QUALCOMM INC52 citations98
US9140747B2Sep 22, 2015
Sense amplifier offset voltage reduction
QUALCOMM INC54 citations97
US10381060B2Aug 13, 2019
High-speed, low power spin-orbit torque (SOT) assisted spin-transfer torque magnetic random access memory (STT-MRAM) bit cell array
QUALCOMM INC25 citations94
US10311930B1Jun 4, 2019
One-time programming (OTP) magneto-resistive random access memory (MRAM) bit cells in a physically unclonable function (PUF) memory in breakdown to a memory state from a previous read operation to provide PUF operations
QUALCOMM INC29 citations94
US10319425B1Jun 11, 2019
Offset-cancellation sensing circuit (OCSC)-based non-volatile (NV) memory circuits
QUALCOMM INC15 citations85
US10636962B2Apr 28, 2020
Spin-orbit torque (SOT) magnetic tunnel junction (MTJ) (SOT-MTJ) devices employing perpendicular and in-plane free layer magnetic anisotropy to facilitate perpendicular magnetic orientation switching, suitable for use in memory systems for storing data
QUALCOMM INC9 citations84
US10460780B2Oct 29, 2019
Magneto-resistive random access memory (MRAM) employing an integrated physically unclonable function (PUF) memory
QUALCOMM INC7 citations84
US10249814B1Apr 2, 2019
Dynamic memory protection
QUALCOMM INC8 citations84
US10115444B1Oct 30, 2018
Data bit inversion tracking in cache memory to reduce data bits written for write operations
QUALCOMM INC9 citations84
US9633706B1Apr 25, 2017
Voltage self-boosting circuit for generating a boosted voltage for driving a word line write in a memory array for a memory write operation
QUALCOMM INC9 citations84
US9583171B2Feb 28, 2017
Write driver circuits for resistive random access memory (RAM) arrays
QUALCOMM INC10 citations84
US9401226B1Jul 26, 2016
MRAM initialization devices and methods
QUALCOMM INC11 citations84
US9275714B1Mar 1, 2016
Read operation of MRAM using a dummy word line
QUALCOMM INC13 citations84
US9251881B2Feb 2, 2016
System and method to trim reference levels in a resistive memory
QUALCOMM INC14 citations84
US9800271B2Oct 24, 2017
Error correction and decoding
QUALCOMM INC8 citations83
US10290340B1May 14, 2019
Offset-canceling (OC) write operation sensing circuits for sensing switching in a magneto-resistive random access memory (MRAM) bit cell in an MRAM for a write operation
QUALCOMM INC11 citations82
US9653183B1May 16, 2017
Shared built-in self-analysis of memory systems employing a memory array tile architecture
QUALCOMM INC2 citations73
US9612908B2Apr 4, 2017
Performing memory data scrubbing operations in processor-based memory in response to periodic memory controller wake-up periods
QUALCOMM INC3 citations73
US9583170B2Feb 28, 2017
Adjusting resistive memory write driver strength based on a mimic resistive memory write operation
QUALCOMM INC6 citations73
US9552244B2Jan 24, 2017
Real time correction of bit failure in resistive memory
QUALCOMM INC5 citations73
US9455014B1Sep 27, 2016
Adjusting resistive memory write driver strength based on write error rate (WER) to improve WER yield, and related methods and systems
QUALCOMM INC4 citations73
US9431129B2Aug 30, 2016
Variable read delay system
QUALCOMM INC5 citations73
US9183082B2Nov 10, 2015
Error detection and correction of one-time programmable elements
QUALCOMM INC6 citations73
US9135975B2Sep 15, 2015
Write pulse width scheme in a resistive memory
QUALCOMM INC6 citations73
US10263645B2Apr 16, 2019
Error correction and decoding
QUALCOMM INC4 citations72
US9262263B2Feb 16, 2016
Bit recovery system
QUALCOMM INC2 citations63
US9153307B2Oct 6, 2015
System and method to provide a reference cell
QUALCOMM INC3 citations63
US8913450B2Dec 16, 2014
Memory cell array with reserved sector for storing configuration information
QUALCOMM INC2 citations63
US9336847B2May 10, 2016
Method and apparatus for generating a reference for use with a magnetic tunnel junction
QUALCOMM INC0 citations52
US9495261B2Nov 15, 2016
Systems and methods for reducing memory failures
QUALCOMM INC0 citations51
US10740017B2Aug 11, 2020
Dynamic memory protection
QUALCOMM INC0 citations41
US9753874B2Sep 5, 2017
Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems
QUALCOMM INC0 citations41