Inventor
TERRY DAVID R
US50 patents
⚠️ This page may combine multiple inventors who share the name “TERRY DAVID R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
47 patentsUS9524171B1Dec 20, 2016
Split-level history buffer in a computer processing unit
IBM4 citations84
US9985656B2May 29, 2018
Generating ECC values for byte-write capable registers
IBM7 citations83
US9985655B2May 29, 2018
Generating ECC values for byte-write capable registers
IBM6 citations83
US10241800B2Mar 26, 2019
Split-level history buffer in a computer processing unit
IBM1 citations73
US10073699B2Sep 11, 2018
Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture
IBM5 citations73
US9747217B2Aug 29, 2017
Distributed history buffer flush and restore handling in a parallel slice design
IBM3 citations73
US9740620B2Aug 22, 2017
Distributed history buffer flush and restore handling in a parallel slice design
IBM5 citations73
US10176038B2Jan 8, 2019
Partial ECC mechanism for a byte-write capable register
IBM2 citations72
US9928128B2Mar 27, 2018
In-pipe error scrubbing within a processor core
IBM6 citations72
US9921833B2Mar 20, 2018
Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor
IBM3 citations72
US9870045B2Jan 16, 2018
Reducing power consumption in a multi-slice computer processor
IBM3 citations72
US9639418B2May 2, 2017
Parity protection of a register
IBM4 citations72
US10248426B2Apr 2, 2019
Direct register restore mechanism for distributed history buffers
IBM3 citations71
US9959123B2May 1, 2018
Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor
IBM2 citations71
US10268482B2Apr 23, 2019
Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction
IBM2 citations69
US9940139B2Apr 10, 2018
Split-level history buffer in a computer processing unit
IBM1 citations63
US9851979B2Dec 26, 2017
Split-level history buffer in a computer processing unit
IBM1 citations63
US11138050B2Oct 5, 2021
Operation of a multi-slice processor implementing a hardware level transfer of an execution thread
IBM0 citations62
US11093282B2Aug 17, 2021
Register file write using pointers
IBM0 citations62
US10545765B2Jan 28, 2020
Multi-level history buffer for transaction memory in a microprocessor
IBM1 citations62
US10379867B2Aug 13, 2019
Asynchronous flush and restore of distributed history buffer
IBM1 citations62
US10255071B2Apr 9, 2019
Method and apparatus for managing a speculative transaction in a processing unit
IBM1 citations62
US11163568B2Nov 2, 2021
Implementing write ports in register-file array cell
IBM1 citations61
US10909034B2Feb 2, 2021
Issue queue snooping for asynchronous flush and restore of distributed history buffer
IBM0 citations52
US10282205B2May 7, 2019
Method and apparatus for execution of threads on processing slices using a history buffer for restoring architected register data via issued instructions
IBM0 citations52
US10248421B2Apr 2, 2019
Operation of a multi-slice processor with reduced flush and restore latency
IBM0 citations52
US10241790B2Mar 26, 2019
Operation of a multi-slice processor with reduced flush and restore latency
IBM0 citations52
US9971604B2May 15, 2018
History buffer for multiple-field registers
IBM1 citations52
US10671398B2Jun 2, 2020
Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core
IBM0 citations51
US10671399B2Jun 2, 2020
Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core
IBM0 citations51
US10564691B2Feb 18, 2020
Reducing power consumption in a multi-slice computer processor
IBM0 citations51
US10489253B2Nov 26, 2019
On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor
IBM0 citations51
US10318356B2Jun 11, 2019
Operation of a multi-slice processor implementing a hardware level transfer of an execution thread
IBM0 citations51
US10223196B2Mar 5, 2019
ECC scrubbing method in a multi-slice microprocessor
IBM0 citations51
US10209757B2Feb 19, 2019
Reducing power consumption in a multi-slice computer processor
IBM0 citations51
US9928073B2Mar 27, 2018
Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor
IBM0 citations51
US9870039B2Jan 16, 2018
Reducing power consumption in a multi-slice computer processor
IBM0 citations51
US9846614B1Dec 19, 2017
ECC scrubbing in a multi-slice microprocessor
IBM0 citations51
US10140127B2Nov 27, 2018
Operation of a multi-slice processor with selective producer instruction types
IBM0 citations50
US10127047B2Nov 13, 2018
Operation of a multi-slice processor with selective producer instruction types
IBM0 citations50
US9952874B2Apr 24, 2018
Operation of a multi-slice processor with selective producer instruction types
IBM0 citations50
US9952861B2Apr 24, 2018
Operation of a multi-slice processor with selective producer instruction types
IBM0 citations50
US9858078B2Jan 2, 2018
Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor
IBM0 citations50
US10282207B2May 7, 2019
Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction
IBM0 citations48
US10289415B2May 14, 2019
Method and apparatus for execution of threads on processing slices using a history buffer for recording architected register data
IBM0 citations41
US9766975B2Sep 19, 2017
Partial ECC handling for a byte-write capable register
IBM0 citations41
US10296337B2May 21, 2019
Preventing premature reads from a general purpose register
IBM0 citations40