Inventor
RAYADURGAM CHAKRAPANI
IN8 patents
Patents
8 patentsUS7747908B2Jun 29, 2010
System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation
IBM14 citations82
US7661023B2Feb 9, 2010
System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation
IBM9 citations82
US10289512B2May 14, 2019
Persistent command parameter table for pre-silicon device testing
IBM1 citations71
US9892010B2Feb 13, 2018
Persistent command parameter table for pre-silicon device testing
IBM2 citations71
US9619312B2Apr 11, 2017
Persistent command parameter table for pre-silicon device testing
IBM2 citations71
US9524801B2Dec 20, 2016
Persistent command parameter table for pre-silicon device testing
IBM2 citations61
US11868259B2Jan 9, 2024
System coherency protocol
IBM1 citations59
US10901902B2Jan 26, 2021
Efficient inclusive cache management
IBM0 citations50