Inventor
BRANDT UWE
DE28 patents
⚠️ This page may combine multiple inventors who share the name “BRANDT UWE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
24 patentsUS10380033B2Aug 13, 2019
Multi-engine address translation facility
IBM6 citations84
US10380032B2Aug 13, 2019
Multi-engine address translation facility
IBM1 citations73
US10083124B1Sep 25, 2018
Translating virtual memory addresses to physical addresses
IBM6 citations73
US9720764B2Aug 1, 2017
Uncorrectable memory errors in pipelined CPUs
IBM2 citations73
US9886395B2Feb 6, 2018
Evicting cached stores
IBM2 citations72
US9658967B2May 23, 2017
Evicting cached stores
IBM2 citations72
US11036647B2Jun 15, 2021
Suspending translation look-aside buffer purge execution in a multi-processor environment
IBM0 citations62
US10956341B2Mar 23, 2021
Multi-engine address translation facility
IBM0 citations62
US10929312B2Feb 23, 2021
Zone-SDID mapping scheme for TLB purges
IBM0 citations62
US7844871B2Nov 30, 2010
Test interface for memory elements
IBM6 citations61
US10635603B2Apr 28, 2020
Multi-engine address translation facility
IBM0 citations52
US10621105B2Apr 14, 2020
Multi-engine address translation facility
IBM0 citations52
US10353828B2Jul 16, 2019
Zone-SDID mapping scheme for TLB purges
IBM0 citations52
US10353827B2Jul 16, 2019
Zone-SDID mapping scheme for TLB purges
IBM0 citations52
US10698835B2Jun 30, 2020
Suspending translation look-aside buffer purge execution in a multi-processor environment
IBM0 citations51
US10387326B2Aug 20, 2019
Incorporating purge history into least-recently-used states of a translation lookaside buffer
IBM0 citations51
US10353825B2Jul 16, 2019
Suspending translation look-aside buffer purge execution in a multi-processor environment
IBM0 citations51
US10289562B2May 14, 2019
Incorporating purge history into least-recently-used states of a translation lookaside buffer
IBM0 citations51
US10248575B2Apr 2, 2019
Suspending translation look-aside buffer purge execution in a multi-processor environment
IBM0 citations51
US9588893B2Mar 7, 2017
Store cache for transactional memory
IBM0 citations51
US9588894B2Mar 7, 2017
Store cache for transactional memory
IBM0 citations51
US10140217B1Nov 27, 2018
Link consistency in a hierarchical TLB with concurrent table walks
IBM0 citations46
US10127159B1Nov 13, 2018
Link consistency in a hierarchical TLB with concurrent table walks
IBM1 citations46
US8756538B2Jun 17, 2014
Parsing data representative of a hardware design into commands of a hardware design environment
IBM0 citations46