Inventor

RECKTENWALD MARTIN

DE91 patents

⚠️ This page may combine multiple inventors who share the name “RECKTENWALD MARTIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RECKTENWALD MARTIN

IBM

Method, system and computer program product for sampling computer system performance data

Reducing cache transfer overhead in a system

Hierarchical cache structure and handling thereof

Hierarchical cache structure and handling thereof

Operand fetching control as a function of branch confidence

Hierarchical cache structure and handling thereof

Providing accurate time-based counters for scaling operating frequencies of microprocessors

Translation support for a virtual cache

Reducing cache transfer overhead in a system

Cache structure using a logical directory

Reducing cache transfer overhead in a system

Sort and merge instruction for a general-purpose processor

Cache structure using a logical directory

Reducing cache transfer overhead in a system

Reducing cache transfer overhead in a system

Uncorrectable memory errors in pipelined CPUs

Generating time-of-day values without causing execution stalls

Single thread cache miss rate estimation

Systems and methods for accessing cache memory

Hierarchical cache structure and handling thereof

Bits register for synonyms in a memory system

Evicting cached stores

Evicting cached stores

Reducing cache transfer overhead in a system

Computer system software/firmware and a processor unit with a security module

Multilevel cache system

Store buffer for transactional memory

Method and apparatus for dynamic system-level frequency scaling

Translation support for a virtual cache

Saving and restoring machine state between multiple executions of an instruction

Sort and merge instruction for a general-purpose processor

Testing a data coherency algorithm

Selective downstream cache processing for data access

Selective downstream cache processing for data access

Saving and restoring machine state between multiple executions of an instruction

Sharing virtual and real translations in a virtual cache

Testing a data coherency algorithm

Testing a data coherency algorithm

Cache management

Parallel sort accelerator sharing first level processor cache

Hardware sort accelerator sharing first level processor cache

Cache management

Hardware control of CPU hold of a cache line in private cache where cache invalidate bit is reset upon expiration of timer

Controlling storage accesses for merge operations

Hardware mitigation for Spectre and meltdown-like attacks

Translation support for a virtual cache

Saving and restoring machine state between multiple executions of an instruction

Cache structure using a logical directory

Sharing virtual and real translations in a virtual cache

GLOBALFOUNDRIES INC

Handling virtual memory address synonyms in a multi-level cache hierarchy structure