Inventor

LU TAO CHENG

TW145 patents

⚠️ This page may combine multiple inventors who share the name “LU TAO CHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LU TAO CHENG

MACRONIX INT CO LTD

Nonvolatile semiconductor memory cell with electron-trapping erase state and methods for operating the same

Method of controlling multi-state NROM

Method and system for self-convergent erase in charge trapping memory cells

Integrated code and data flash memory

Apparatus and method for programming virtual ground nonvolatile memory cell array without disturbing adjacent cells

Method for fabricating nitride read only memory

SONOS component having high dielectric property

NAND-type non-volatile memory cell and method for operating same

Method of programming and erasing multi-level flash memory

Erasing method for non-volatile memory

Memory erase method and device with optimal data retention for nonvolatile memory

Non-volatile memory and operating method thereof

Erase scheme for non-volatile memory

Method of fabricating a non-volatile memory with a spacer

Method of programming and erasing a SNNNS type non-volatile memory cell

Method of fabricating a sonos device

Multi-level memory cell device and method for self-converged programming

Virtual ground EPROM structure

Method for fabricating a memory device with a floating gate

Overerase protection of memory cells for nonvolatile memory

CMOS structure having dynamic threshold voltage

Method for programming programmable eraseless memory

Electrostatic discharge protection circuit coupled on I/O pad

ESD protection apparatus and method for a high-voltage input pad

RC controlled ESD circuits for mixed-voltage interface

ESD protection apparatus and method for dual-polarity input pad

Method for programming and erasing non-volatile memory with nitride tunneling layer

Trim circuit and method for tuning a current level of a reference cell in a flash memory

ESD device used with high-voltage input pad

Operation method for programming and erasing a data in a P-channel sonos memory cell

Erasing method for p-channel NROM

Substrate pump circuit and method for I/O ESD protection

Device and method for testing mask ROM for bitline to bitline isolation leakage

Method of forming an asymmetric bird&#39;s beak cell for a flash EEPROM

Silicon controlled rectifier structure with guard ring controlled circuit

Silicon controlled rectifier structure with guard ring controlled circuit

Circuit and method for measuring capacitance

Electrostatic discharge input protection for reducing input resistance

Self protected stacked NMOS with non-silicided region to protect mixed-voltage I/O pad from ESD damage

Electrostatic discharge conduction device and mixed power integrated circuits using same

Silicide blocking process to form non-silicided regions on MOS devices

Method for manufacturing a programmable eraseless memory

Nonvolatile memory cell and operating method

Non-volatile flash memory

Nitride read-only memory cell for improving second-bit effect and method for making thereof

Semiconductor device with trench isolation structure

Method to scale down device dimension using spacer to confine buried drain implant

Method of manufacturing metal-oxide semiconductor transistor

(unassigned)

8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate

Method for fabricating a cell structure for mask ROM

Method of forming an asymmetric bird's beak cell for a flash EEPROM