P

Inventor

MILLER ERIC R

US88 patents
⚠️ This page may combine multiple inventors who share the name “MILLER ERIC R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

28 patents
US9620590B1Apr 11, 2017

Nanosheet channel-to-source and drain isolation

IBM105 citations99
US9608065B1Mar 28, 2017

Air gap spacer for metal gates

IBM141 citations99
US9905643B1Feb 27, 2018

Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

IBM28 citations94
US9450095B1Sep 20, 2016

Single spacer for complementary metal oxide semiconductor process flow

IBM24 citations94
US9362179B1Jun 7, 2016

Method to form dual channel semiconductor material fins

IBM41 citations94
US10615269B2Apr 7, 2020

Nanosheet channel-to-source and drain isolation

IBM5 citations84
US10249738B2Apr 2, 2019

Nanosheet channel-to-source and drain isolation

IBM6 citations84
US10074730B2Sep 11, 2018

Forming stacked nanowire semiconductor device

IBM11 citations84
US10043801B2Aug 7, 2018

Air gap spacer for metal gates

IBM5 citations84
US10014391B2Jul 3, 2018

Vertical transport field effect transistor with precise gate length definition

IBM10 citations84
US9786666B2Oct 10, 2017

Method to form dual channel semiconductor material fins

IBM5 citations84
US9728622B1Aug 8, 2017

Dummy gate formation using spacer pull down hardmask

IBM11 citations84
US11239316B2Feb 1, 2022

Semiconductor device and method of forming the semiconductor device

IBM4 citations83
US11127815B2Sep 21, 2021

Semiconductor device and method of forming the semiconductor device

IBM4 citations83
US10381437B2Aug 13, 2019

Semiconductor device and method of forming the semiconductor device

IBM6 citations83
US9917196B1Mar 13, 2018

Semiconductor device and method of forming the semiconductor device

IBM8 citations83
US9443855B1Sep 13, 2016

Spacer formation on semiconductor device

IBM7 citations82
US10833190B2Nov 10, 2020

Super long channel device within VFET architecture

IBM4 citations73
US10553581B2Feb 4, 2020

Air gap spacer for metal gates

IBM1 citations73
US10249762B2Apr 2, 2019

Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

IBM2 citations73
US10083962B2Sep 25, 2018

Fabrication of fin field effect transistors for complementary metal oxide semiconductor devices including separate n-type and p-type source/drains using a single spacer deposition

IBM2 citations73
US9997369B2Jun 12, 2018

Margin for fin cut using self-aligned triple patterning

IBM2 citations73
US9985138B2May 29, 2018

Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

IBM2 citations73
US9893166B2Feb 13, 2018

Dummy gate formation using spacer pull down hardmask

IBM3 citations73
US9754942B2Sep 5, 2017

Single spacer for complementary metal oxide semiconductor process flow

IBM2 citations73
US9536744B1Jan 3, 2017

Enabling large feature alignment marks with sidewall image transfer patterning

IBM5 citations73
US10985025B2Apr 20, 2021

Fin cut profile using fin base liner

IBM0 citations63
US10937810B2Mar 2, 2021

Sub-fin removal for SOI like isolation with uniform active fin height

IBM0 citations63

ARCHIBALD BROS FINE BEVERAGES

5 patents

MATTHEWS INT CORP

3 patents

ARCHIBALD BROTHERS INTERNATION

2 patents

(unassigned)

2 patents

TESSERA INC

2 patents

TESSERA LLC

2 patents

ADEIA SEMICONDUCTOR SOLUTIONS LLC

2 patents

PHOENIX ANALYSIS AND DESIGN TE

1 patent

ACCENTURE GLOBAL SERVICES GMBH

1 patent

RAYTHEON CO

1 patent

ATMEL CORP

1 patent

Showing the top 50 of 88 patents by PatentIndex Score.