Inventor
SHEARER JEFFREY C
US27 patents
Patents
27 patentsUS9450095B1Sep 20, 2016
Single spacer for complementary metal oxide semiconductor process flow
IBM24 citations94
US9318574B2Apr 19, 2016
Method and structure for enabling high aspect ratio sacrificial gates
IBM16 citations92
US10074730B2Sep 11, 2018
Forming stacked nanowire semiconductor device
IBM11 citations84
US9842739B2Dec 12, 2017
Method and structure for enabling high aspect ratio sacrificial gates
IBM8 citations84
US9659779B2May 23, 2017
Method and structure for enabling high aspect ratio sacrificial gates
IBM7 citations84
US9859212B1Jan 2, 2018
Multi-level air gap formation in dual-damascene structure
IBM4 citations83
US10629698B2Apr 21, 2020
Method and structure for enabling high aspect ratio sacrificial gates
IBM1 citations73
US10249753B2Apr 2, 2019
Gate cut on a vertical field effect transistor with a defined-width inorganic mask
IBM4 citations73
US9882048B2Jan 30, 2018
Gate cut on a vertical field effect transistor with a defined-width inorganic mask
IBM5 citations73
US9754942B2Sep 5, 2017
Single spacer for complementary metal oxide semiconductor process flow
IBM2 citations73
US9536744B1Jan 3, 2017
Enabling large feature alignment marks with sidewall image transfer patterning
IBM5 citations73
US11222820B2Jan 11, 2022
Self-aligned gate cap including an etch-stop layer
IBM2 citations72
US10586733B2Mar 10, 2020
Multi-level air gap formation in dual-damascene structure
IBM1 citations72
US10224239B2Mar 5, 2019
Multi-level air gap formation in dual-damascene structure
IBM3 citations72
US9748146B1Aug 29, 2017
Single spacer for complementary metal oxide semiconductor process flow
IBM1 citations63
US12464809B2Nov 4, 2025
Vertical field effect transistor with minimal contact to gate erosion
IBM0 citations62
US10796957B2Oct 6, 2020
Buried contact to provide reduced VFET feature-to-feature tolerance requirements
IBM1 citations62
US11257716B2Feb 22, 2022
Self-aligned gate cap including an etch-stop layer
IBM0 citations61
US11605717B2Mar 14, 2023
Wrapped-around contact for vertical field effect transistor top source-drain
IBM0 citations52
US10804148B2Oct 13, 2020
Buried contact to provide reduced VFET feature-to-feature tolerance requirements
IBM0 citations52
US10446452B2Oct 15, 2019
Method and structure for enabling controlled spacer RIE
IBM0 citations52
US10396181B2Aug 27, 2019
Forming stacked nanowire semiconductor device
IBM0 citations52
US10304692B1May 28, 2019
Method of forming field effect transistor (FET) circuits, and forming integrated circuit (IC) chips with the FET circuits
IBM0 citations52
US10256326B2Apr 9, 2019
Forming stacked nanowire semiconductor device
IBM0 citations52
US9716184B2Jul 25, 2017
Enabling large feature alignment marks with sidewall image transfer patterning
IBM0 citations52
US9627277B2Apr 18, 2017
Method and structure for enabling controlled spacer RIE
IBM0 citations52
US10204827B2Feb 12, 2019
Multi-level air gap formation in dual-damascene structure
IBM0 citations51