Inventor

TEEHAN SEAN

US70 patents

⚠️ This page may combine multiple inventors who share the name “TEEHAN SEAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TEEHAN SEAN

IBM

Nanosheet channel-to-source and drain isolation

Air gap spacer for metal gates

Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

Single spacer for complementary metal oxide semiconductor process flow

Method to form dual channel semiconductor material fins

Method and structure for enabling high aspect ratio sacrificial gates

Nanosheet channel-to-source and drain isolation

Nanosheet channel-to-source and drain isolation

Fin patterns with varying spacing without fin cut

Forming stacked nanowire semiconductor device

Air gap spacer for metal gates

Vertical transport field effect transistor with precise gate length definition

Method and structure for enabling high aspect ratio sacrificial gates

Method to form dual channel semiconductor material fins

Dummy gate formation using spacer pull down hardmask

Method and structure for enabling high aspect ratio sacrificial gates

Semiconductor device and method of forming the semiconductor device

Semiconductor device and method of forming the semiconductor device

Semiconductor device and method of forming the semiconductor device

Semiconductor device and method of forming the semiconductor device

Super long channel device within VFET architecture

Method and structure for enabling high aspect ratio sacrificial gates

Air gap spacer for metal gates

Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

Fin patterns with varying spacing without fin cut

Fabrication of fin field effect transistors for complementary metal oxide semiconductor devices including separate n-type and p-type source/drains using a single spacer deposition

Margin for fin cut using self-aligned triple patterning

Fin patterns with varying spacing without fin cut

Fin patterns with varying spacing without fin cut

Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

Electrically conductive interconnect including via having increased contact surface area

Dummy gate formation using spacer pull down hardmask

Method and structure to enable dual channel fin critical dimension control

Single spacer for complementary metal oxide semiconductor process flow

Electrically conductive interconnect including via having increased contact surface area

Enabling large feature alignment marks with sidewall image transfer patterning

Sub-fin removal for SOI like isolation with uniform active fin height

Fabrication of fin field effect transistors for complementary metal oxide semiconductor devices including separate n-type and p-type source/drains using a single spacer deposition

Super long channel device within VFET architecture

Fin patterns with varying spacing without Fin cut

Single spacer for complementary metal oxide semiconductor process flow

Semiconductor device and method of forming the semiconductor device

Semiconductor device and method of forming the semiconductor device

Cyclic etch process to remove dummy gate oxide layer for fin field effect transistor fabrication

TESSERA INC

Nanosheet channel-to-source and drain isolation

Air gap spacer for metal gates

TESSERA LLC

Nanosheet channel-to-source and drain isolation

Air gap spacer for metal gates

ADEIA SEMICONDUCTOR SOLUTIONS LLC

Air gap spacer for metal gates

Nanosheet channel-to-source and drain isolation