Inventor
REICHART JOHANNES C
US17 patents
Patents
17 patentsUS11775445B2Oct 3, 2023
Translation support for a virtual cache
IBM2 citations73
US9934343B2Apr 3, 2018
System and method for generation of an integrated circuit design
IBM3 citations71
US12141076B2Nov 12, 2024
Translation support for a virtual cache
IBM0 citations62
US11169922B2Nov 9, 2021
Method and arrangement for saving cache power
IBM0 citations62
US10997079B2May 4, 2021
Method and arrangement for saving cache power
IBM0 citations62
US10606762B2Mar 31, 2020
Sharing virtual and real translations in a virtual cache
IBM1 citations62
US10169234B2Jan 1, 2019
Translation lookaside buffer purging with concurrent cache updates
IBM1 citations61
US10831674B2Nov 10, 2020
Translation support for a virtual cache
IBM0 citations52
US10810134B2Oct 20, 2020
Sharing virtual and real translations in a virtual cache
IBM0 citations52
US10698836B2Jun 30, 2020
Translation support for a virtual cache
IBM0 citations52
US10740240B2Aug 11, 2020
Method and arrangement for saving cache power
IBM0 citations51
US10678974B2Jun 9, 2020
System and method for generation of an integrated circuit design
IBM0 citations51
US10572617B2Feb 25, 2020
System and method for generation of an integrated circuit design
IBM0 citations51
US10528472B2Jan 7, 2020
Method and arrangement for saving cache power
IBM0 citations51
US10229061B2Mar 12, 2019
Method and arrangement for saving cache power
IBM0 citations51
US9928321B2Mar 27, 2018
System and method for generation of an integrated circuit design
IBM0 citations51
US10169233B2Jan 1, 2019
Translation lookaside buffer purging with concurrent cache updates
IBM0 citations50