Inventor

SERRANO MAURICIO J

US35 patents

⚠️ This page may combine multiple inventors who share the name “SERRANO MAURICIO J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SERRANO MAURICIO J

IBM

Method for optimizing creation and destruction of objects in computer programs

Method for compiling program components in a mixed static and dynamic environment

Method for optimizing locks in computer programs

System for target branch prediction using correlation of local target histories including update inhibition for inefficient entries

Mechanism for data cache replacement based on region policies

Branch prediction using multiple versions of history data

Target branch prediction using a plurality of tables

Techniques for dynamic sequential instruction prefetching

Redundant transactions for detection of timing sensitive errors

Dual phase matrix-vector multiplication system

Predicting indirect branches using problem branch filtering and pattern cache

Branch prediction using multiple versions of history data

Transactions for checkpointing and reverse execution

Hardware-assisted program trace collection with selectable call-signature capture

Preferred write-mostly data cache replacement policies

Dual phase matrix-vector multiplication system

Dynamic sequential instruction prefetching

Compressed indirect prediction caches

Instruction prefetching in a computer processor using a prefetch prediction vector

Wide vector execution in single thread mode for an out-of-order processor

Wide vector execution in single thread mode for an out-of-order processor

Branch prediction using multiple versions of history data

Branch prediction using multiple versions of history data

Detection of hardware errors using periodically synchronized redundant transactions and comparing results from cores of a multi-core processor

Detection of hardware errors using redundant transactions for system test

Redundant transactions for detection of timing sensitive errors

Reducing memory access latency in scatter/gather operations

Instruction prefetching in a computer processor using a prefetch prediction vector

Switching matrix representation for an incremental algorithm computing connected components

Tracking long GHV in high performance out-of-order superscalar processors

SERRANO MAURICIO J

Tracking a programs calling context using a hybrid code signature

Data placement optimization using data context collected during garbage collection

INTEL CORP

Methods and apparatus to dynamically insert prefetch instructions based on garbage collector analysis and layout of objects

Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis

CASTANOS JOSE G

Adaptive next-executing-cycle trace selection for trace-driven code optimizers