Inventor

KUO TIN-HAO

TW230 patents

⚠️ This page may combine multiple inventors who share the name “KUO TIN-HAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KUO TIN-HAO

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor packages and methods of forming the same

Integrated fan-out stacked package with fan-out redistribution layer (RDL)

Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors

Method of manufacturing an integrated stacked package with a fan-out redistribution layer (RDL) and a same encapsulating process

Semicondcutor package and method of manufacturing the same

Cross-wafer RDLs in constructed wafers

Cross-wafer RDLs in constructed wafers

Integrated circuit package and method

Dummy dies for reducing warpage in packages

Semiconductor package and method

Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors

Three-dimension large system integration

Chip package and method of forming the same

Integrated fan-out device, 3D-IC system, and method

Integrated circuit package and method

Multi-chip semiconductor package

Cross-wafer RDLs in constructed wafers

Chip package and method of forming the same

Semiconductor structure with conductive structure

Dummy flip chip bumps for reducing stress

Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors

Contact area design for solder bonding

Substrate design with balanced metal and solder resist density

Conical-shaped or tier-shaped pillar connections

Conductive contacts having varying widths and method of manufacturing same

Integrated fan-out package and method of fabricating the same

Contact area design for solder bonding

Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices

Dual-sided integrated fan-out package

Method of forming bump structure having a side recess and semiconductor structure including the same

Interconnection structure and method of forming same

Semiconductor package and manufacturing method thereof

IPD modules with flexible connection scheme in packaging

TAIWAN SEMICONDUCTOR MFG

Conductive contacts having varying widths and method of manufacturing same

Dummy flip chip bumps for reducing stress

Scheme for connector site spacing and resulting structures

Substrate design with balanced metal and solder resist density

Bump structure having a single side recess

Pillar structure having a non-planar surface for semiconductor devices

Pillar structure having a non-planar surface for semiconductor devices

Pillar structure having a non-planar surface for semiconductor devices

KUO TIN-HAO

Conical-shaped or tier-shaped pillar connections

Pillar structure having a non-planar surface for semiconductor devices

HU YEN-CHANG

Methods and apparatus for package on package devices with reversed stud bump through via interconnections

SHIEH YUH CHERN

Reduced-stress bump-on-trace (BOT) structures

TSAI PEI-CHUN

Connecting function chips to a package to form package-on-package

CHANG CHIH-HORNG

Bump structures

CHEN YU-FENG

Extending metal traces in bump-on-trace structures

WU SHENG-YU

Dummy flip chip bumps for reducing stress

SHEN CHENG HUNG

Substrate stand-offs for semiconductor devices