Inventor
DZIOBKOWSKI CHESTER T
US13 patents
Patents
13 patentsUS7402532B2Jul 22, 2008
Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer
IBM28 citations92
US7271455B2Sep 18, 2007
Formation of fully silicided metal gate using dual self-aligned silicide process
IBM20 citations92
US7122472B2Oct 17, 2006
Method for forming self-aligned dual fully silicided gates in CMOS devices
IBM23 citations92
US7102232B2Sep 5, 2006
Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer
IBM19 citations92
US7067368B1Jun 27, 2006
Method for forming self-aligned dual salicide in CMOS technologies
IBM17 citations92
US6916729B2Jul 12, 2005
Salicide formation method
IBM16 citations83
US7112481B2Sep 26, 2006
Method for forming self-aligned dual salicide in CMOS technologies
IBM5 citations74
US7820559B2Oct 26, 2010
Structure to improve adhesion between top CVD low-K dielectric and dielectric capping layer
IBM4 citations72
US6046457AApr 4, 2000
Charged particle beam apparatus having anticontamination means
IBM8 citations70
US7064025B1Jun 20, 2006
Method for forming self-aligned dual salicide in CMOS technologies
IBM4 citations63
US7785999B2Aug 31, 2010
Formation of fully silicided metal gate using dual self-aligned silicide process
IBM3 citations62
US7910484B2Mar 22, 2011
Method for preventing backside defects in dielectric layers formed on semiconductor substrates
IBM1 citations50
US7223691B2May 29, 2007
Method of forming low resistance and reliable via in inter-level dielectric interconnect
IBM0 citations48