Inventor

FANG SUNFEI

US40 patents

⚠️ This page may combine multiple inventors who share the name “FANG SUNFEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FANG SUNFEI

IBM

Metal gate MOSFET by full semiconductor metal alloy conversion

Self-aligned dual segment liner and method of manufacturing the same

Formation of fully silicided metal gate using dual self-aligned silicide process

Method for forming self-aligned dual fully silicided gates in CMOS devices

Method for forming self-aligned dual salicide in CMOS technologies

Dual stress memory technique method and related structure

CMOS devices with hybrid channel orientations, and methods for fabricating the same using faceted epitaxy

Extended raised source/drain structure for enhanced contact area and method for forming extended raised source/drain structure

Salicide formation method

Method for forming self-aligned metal silicide contacts

Method for forming self-aligned metal silicide contacts

Forming conductive stud for semiconductive devices

Fully silicided field effect transistors

Method for forming self-aligned dual salicide in CMOS technologies

Self-forming metal silicide gate for CMOS devices

Asymmetric semiconductor devices and method of fabricating

Silicided polysilicon spacer for enhanced contact area

Field effect transistors (FETs) with multiple and/or staircase silicide

Method for forming self-aligned dual salicide in CMOS technologies

Formation of fully silicided metal gate using dual self-aligned silicide process

Post-silicide spacer removal

Non-conformal stress liner for enhanced MOSFET performance

Forming conductive stud for semiconductive devices

Field effect transistors (FETs) with multiple and/or staircase silicide

Pre-silicide spacer removal

Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors

Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors

Method of forming low resistance and reliable via in inter-level dielectric interconnect

Self-aligned silicide bottom plate for eDRAM applications by self-diffusing metal in CVD/ALD metal process

SAMSUNG ELECTRONICS CO LTD

Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon

Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques

Test structure of semiconductor device

FANG SUNFEI

Structure and method to improve threshold voltage of MOSFETS including a high K dielectric

Shallow trench isolation for device including deep trench capacitors

Structure and method to improve threshold voltage of MOSFETs including a high k dielectric

CHIDAMBARRAO DURESETI

Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same

Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same

INFINEON TECHNOLOGIES AG

Method of forming organic spacers and using organic spacers to form semiconductor device features

Method of cleaning an inter-level dielectric interconnect

INFINEON TECHNOLOGIES CORP

Simultaneous native oxide removal and metal neutral deposition method