Inventor

JAMMY RAJARAO

US77 patents

⚠️ This page may combine multiple inventors who share the name “JAMMY RAJARAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAMMY RAJARAO

IBM

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics

High density chip carrier with integrated passive devices

High density chip carrier with integrated passive devices

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics

Quantum conductive barrier for contact to shallow diffusion region

Reduction of polysilicon stress in trench capacitors

Highly conformal titanium nitride deposition process for high aspect ratio structures

Variable stoichiometry silicon nitride barrier films for tunable etch selectivity and enhanced hyrogen permeability

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics

Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics

Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS

Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide

Field effect transistor with etched-back gate dielectric

Nitrided STI liner oxide for reduced corner device impact on vertical device performance

Trench capacitors with reduced polysilicon stress

Method for forming junction on insulator (JOI) structure

DRAM trench

Introduction of metal impurity to change workfunction of conductive electrodes

Formation of fully silicided metal gate using dual self-aligned silicide process

Metal carbide gate structure and method of fabrication

Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric

Pitcher-shaped active area for field effect transistor and method of forming same

High performance logic and high density embedded dram with borderless contact and antispacer

Method and structure for salicide trench capacitor plate electrode

Process flow for capacitance enhancement in a DRAM trench

Method of fabricating SiO2 spacers and annealing caps

Semi-insulating diffusion barrier for low-resistivity gate conductors

Semiconductor memory device with reduced orientation-dependent oxidation in trench structures

Process for fabricating a uniform gate oxide of a vertical transistor

Low threshold voltage semiconductor device with dual threshold voltage control means

Replacement metal gate transistor with metal-rich silicon layer and method for making the same

Integration scheme enhancing deep trench capacitance in semiconductor integrated circuit devices

Method of forming metal/high-k gate stacks with high mobility

Filling high aspect ratio isolation structures with polysilazane based material

Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices

Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow

Low threshold voltage semiconductor device with dual threshold voltage control means

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high K dielectrics

CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials

Metal carbide gate structure and method of fabrication

Field effect transistor including damascene gate with an internal spacer structure

Introduction of metal impurity to change workfunction of conductive electrodes

Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow

Formation of self-aligned buried strap connector

Pedestal collar structure for higher charge retention time in trench-type DRAM cells

Trench electrode with intermediate conductive barrier layer

High performance logic and high density embedded dram with borderless contact and antispacer

INFINEON TECHNOLOGIES AG

Low resistivity deep trench fill for DRAM and EDRAM applications

BOJARCZUK JR NESTOR A

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics