Inventor

NARAYANAN VIJAY

US254 patents

⚠️ This page may combine multiple inventors who share the name “NARAYANAN VIJAY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NARAYANAN VIJAY

IBM

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics

Method for forming metal replacement gate of high performance

Dual channel structures with multiple threshold voltages

Planar and non-planar CMOS devices with multiple tuned threshold voltages

Removal of charged defects from metal oxide-gate stacks

Metal gate CMOS with at least a single gate metal and dual gate dielectrics

Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics

Method of forming lattice-matched structure on silicon and structure formed thereby

Ferroelectric gate dielectric with scaled interfacial layer for steep sub-threshold slope field-effect transistor

High-K gate dielectric and metal gate conductor stack for planar field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material

Method to improve reliability of replacement gate device

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics

Semiconductor device having dual metal gates and method of manufacture

Techniques for enabling multiple Vt devices using high-K metal gate stacks

Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics

Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS

Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide

Field effect transistor with etched-back gate dielectric

Resistive switching memory stack for three-dimensional structure

Scavenging metal stack for a high-k gate dielectric

Fabrication of a CMOS structure with a high-k dielectric layer oxidizing an aluminum layer in PFET region

Introduction of metal impurity to change workfunction of conductive electrodes

CMOS transistors with differential oxygen content high-k dielectrics

Dual metal gate self-aligned integration

Semiconductor structure including mixed rare earth oxide formed on silicon

Formation of fully silicided metal gate using dual self-aligned silicide process

Method of forming a tantalum-containing gate electrode structure

CMOS silicide metal gate integration

Low threshold voltage semiconductor device with dual threshold voltage control means

Method of forming metal/high-k gate stacks with high mobility

Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device

Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device

Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device

Conformal replacement gate electrode for short channel devices

Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology

Protection of high-K dielectric during reliability anneal on nanosheet structures

Dual channel CMOS having common gate stacks

Patterned gate dielectrics for III-V-based CMOS circuits

High-K spacer for extension-free CMOS devices with high mobility channel materials

CHANG JOSEPHINE B

Multiple Vt field-effect transistor devices

Multiple Vt field-effect transistor devices

GLOBALFOUNDRIES INC

Semiconductor devices with varying threshold voltage and fabrication methods thereof

U S BANK NAT ASSOCIATION

Mobile check deposit

ANDO TAKASHI

Low threshold voltage CMOS device

FRANK MARTIN M

Techniques for enabling multiple Vt devices using high-K metal gate stacks

FAIR ISSAC CORP

Fast accurate fuzzy matching

BRULEY JOHN

Reliable physical unclonable function for device authentication

BOJARCZUK JR NESTOR A

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics