Inventor

PARUCHURI VAMSI

US21 patents

⚠️ This page may combine multiple inventors who share the name “PARUCHURI VAMSI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARUCHURI VAMSI

IBM

Locally raised epitaxy for improved contact by local silicon capping during trench silicide processings

Fabrication of a CMOS structure with a high-k dielectric layer oxidizing an aluminum layer in PFET region

Formation of fully silicided metal gate using dual self-aligned silicide process

Self-aligned CMOS structure with dual workfunction

Gate effective-workfunction modification for CMOS

Low power circuit structure with metal gate and high-k dielectric

Low power circuit structure with metal gate and high-k dielectric

Method to fabricate metal gate high-k devices

Formation of fully silicided metal gate using dual self-aligned silicide process

Dielectric spacer removal

Simple low power circuit structure with metal gate and high-k dielectric

Metal gate high-K devices having a layer comprised of amorphous silicon

Cyclical physical vapor deposition of dielectric layers

ASM IP HOLDING BV

Selective passivation and selective deposition

Selective passivation and selective deposition

Selective passivation and selective deposition

Selective passivation and selective deposition

GLOBALFOUNDRIES INC

Locally raised epitaxy for improved contact by local silicon capping during trench silicide processings

LIN WEI

Corrosion/etching protection in integration circuit fabrications

DORIS BRUCE B

Threshold adjustment for high-K gate dielectric CMOS

PARK DAE-GYU

Gate effective-workfunction modification for CMOS