Inventor

SHAHIDI GHAVAM G

US337 patents

⚠️ This page may combine multiple inventors who share the name “SHAHIDI GHAVAM G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHAHIDI GHAVAM G

IBM

Ultra-thin body super-steep retrograde well (SSRW) FET devices

Patterned SOI regions in semiconductor chips

Process of making densely patterned silicon-on-insulator (SOI) region on a wafer

Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications

Two-device memory cell on SOI for merged logic and memory applications

Active matrix using hybrid integrated circuit and bipolar transistor

Dense finFET SRAM

Integration of dual workfunction metal gate CMOS devices

Double SOI device with recess etch and epitaxy

Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal

FinFET structures having silicon germanium and silicon channels

Distributed decoupling capacitor

Integrating active matrix inorganic light emitting diodes for display devices

Lateral heterojunction bipolar transistors

High-performance FETs with embedded stressors

Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates

Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal

Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal

Patterned SOI by oxygen implantation and annealing

SOI transistor with polysilicon seed

Densely patterned silicon-on-insulator (SOI) region on a wafer

MOSFET structure with ultra-low K spacer

Structure and method of integrating compound and elemental semiconductors for high-performance CMOS

Formation of fully silicided metal gate using dual self-aligned silicide process

CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture

CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture

Formation of patterned silicon-on-insulator (SOI)/silicon-on-nothing (SON) composite structure by porous Si engineering

Patterned SOI regions on semiconductor chips

SOI MOSFETS exhibiting reduced floating-body effects

CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufacture

Integrated circuits with reduced substrate capacitance

Method of integrating substrate contact on SOI wafers with STI process

Process of making buried capacitor for silicon-on-insulator structure

Buried capacitor for silicon-on-insulator structure

SOI lateral bipolar transistor with edge-strapped base contact and method of fabricating same

Monolithic integration of heterojunction solar cells

Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology

P-FET with strained silicon-germanium channel

Active matrix OLED display with normally-on thin-film transistors

Monolithically integrated high voltage photovoltaics and light emitting diode with textured surface

Monolithically integrated high voltage photovoltaics and light emitting diode with textured surface

CHENG KANGGUO

Stressed Fin-FET devices with low contact resistance

Stressed Fin-FET devices with low contact resistance

Hybrid FinFET/planar SOI FETs

Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped source and drain regions formed by a single mask

BEDELL STEPHEN W

Integrating active matrix inorganic light emitting diodes for display devices

Strained CMOS device, circuit and method of fabrication

Breakdown voltage multiplying integration scheme

BOOTH JR ROGER A

Method and structure for forming high performance MOS capacitor along with fully depleted semiconductor on insulator devices on the same chip

HEKMATSHOAR TABARI BAHMAN

Low-temperature selective epitaxial growth of silicon for device integration