Inventor
MARR DEBORAH
US18 patents
Patents
18 patentsUS10146738B2Dec 4, 2018
Hardware accelerator architecture for processing very-sparse and hyper-sparse matrix data
INTEL CORP43 citations94
US11373088B2Jun 28, 2022
Machine learning accelerator mechanism
INTEL CORP28 citations92
US6675282B2Jan 6, 2004
System and method for employing a global bit for page sharing in a linear-addressed cache
INTEL CORP29 citations92
US10776110B2Sep 15, 2020
Apparatus and method for adaptable and efficient lane-wise tensor processing
INTEL CORP20 citations91
US10180928B2Jan 15, 2019
Heterogeneous hardware accelerator architecture for processing sparse matrix data with skewed non-zero distributions
INTEL CORP15 citations85
US11636327B2Apr 25, 2023
Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanism
INTEL CORP6 citations83
US11216722B2Jan 4, 2022
Hardware accelerator template and design framework for implementing recurrent neural networks
INTEL CORP5 citations73
US6560690B2May 6, 2003
System and method for employing a global bit for page sharing in a linear-addressed cache
INTEL CORP8 citations73
US10387037B2Aug 20, 2019
Microarchitecture enabling enhanced parallelism for sparse linear algebra operations having write-to-read dependencies
INTEL CORP5 citations72
US10372507B2Aug 6, 2019
Compute engine architecture to support data-parallel loops with reduction operations
INTEL CORP2 citations72
US12014265B2Jun 18, 2024
Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanism
INTEL CORP1 citations71
US10915328B2Feb 9, 2021
Apparatus and method for a high throughput parallel co-processor and interconnect with low offload latency
INTEL CORP3 citations71
US12039435B2Jul 16, 2024
Machine learning accelerator mechanism
INTEL CORP1 citations70
US11328037B2May 10, 2022
Memory-size- and bandwidth-efficient method for feeding systolic array matrix multipliers
INTEL CORP5 citations69
US12417380B2Sep 16, 2025
Machine learning accelerator mechanism
INTEL CORP0 citations60
US12380326B2Aug 5, 2025
Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanism
INTEL CORP0 citations60
US10831505B2Nov 10, 2020
Architecture and method for data parallel single program multiple data (SPMD) execution
INTEL CORP0 citations50
US11416248B2Aug 16, 2022
Method and system for efficient floating-point compression
INTEL CORP0 citations49