Inventor

CHIRCA KAI

US123 patents

⚠️ This page may combine multiple inventors who share the name “CHIRCA KAI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHIRCA KAI

TEXAS INSTRUMENTS INC

Highly integrated scalable, flexible DSP megamodule architecture

Highly integrated scalable, flexible DSP megamodule architecture

Multicore bus architecture with non-blocking high performance transaction credit system

Multicore, multibank, fully concurrent coherence controller

Multicore, multibank, fully concurrent coherence controller

Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion

Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC

Highly integrated scalable, flexible DSP megamodule architecture

Virtual network pre-arbitration for deadlock avoidance and enhanced performance

Virtual network pre-arbitration for deadlock avoidance and enhanced performance

Configurable cache for coherent system

Multicore shared cache operation engine

Secure master and secure guest endpoint security firewall

Distributed error detection and correction with hamming code handoff

Multicore shared cache operation engine

Multicore shared cache operation engine

Nested loop control

Streaming engine with deferred exception reporting

Secure master and secure guest endpoint security firewall

Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems

Hazard detection and elimination for coherent endpoint allowing out-of-order execution

Exit history based branch prediction

Distributed error detection and correction with hamming code handoff

Multi-processor bridge with cache allocate awareness

Delayed snoop for improved multi-process false sharing parallel thread performance

Multicore shared cache operation engine

Credit aware central arbitration for multi-endpoint, multi-core system

Multicore, multibank, fully concurrent coherence controller

Multicore shared cache operation engine

Cache coherence shared state suppression

Highly integrated scalable, flexible DSP megamodule architecture

Multi-processor bridge with cache allocate awareness

Delayed snoop for improved multi-process false sharing parallel thread performance

Configurable cache for multi-endpoint heterogeneous coherent system

Mechanism for interrupting and resuming execution on an unprotected pipeline processor

Virtual network pre-arbitration for deadlock avoidance and enhanced performance

Cache coherence shared state suppression

User mode event handling

Streaming engine with deferred exception reporting

Credit aware central arbitration for multi-endpoint, multi-core system

Multicore, multibank, fully concurrent coherence controller

Multi-processor, multi-domain, multi-protocol, cache coherent, speculation aware shared memory and interconnect

Configurable cache for multi-endpoint heterogeneous coherent system

CHIRCA KAI

Multilayer arbitration for access to multiple destinations

Speculation-aware memory controller arbiter

Slot/sub-slot prefetch architecture for multiple memory requestors

Memory controller with automatic error detection and correction

ANDERSON TIMOTHY D

Variable line size prefetcher for multiple memory requestors

Predictive sequential prefetching for data caching

SANDBRIDGE TECHNOLOGIES INC

Arithmetic circuit with balanced logic levels for low-power operation