Inventor

MOZAK CHRISTOPHER P

US64 patents

⚠️ This page may combine multiple inventors who share the name “MOZAK CHRISTOPHER P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOZAK CHRISTOPHER P

INTEL CORP

Row hammer refresh command

Row hammer refresh command

Row hammer refresh command

Refresh rate performance based on in-system weak bit detection

Memory link training

Multiple rank high bandwidth memory

Training for command/address/control/clock delays under uncertain initial conditions and for mapping swizzled data to command/address signals

Efficiently training memory device chip select control

Memory subsystem I/O performance based on in-system empirical testing

Efficiently training memory device chip select control

Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines

Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines

Timing control for unmatched signal receiver

Periodic training for unmatched signal receiver

Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system

Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system

Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system

Memory subsystem data bus stress testing

Functional memory array testing with a transaction-level test engine

Transaction-level testing of memory I/O and memory device

Power efficient, single-ended termination using on-die voltage supply

Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines

Timing control for unmatched signal receiver

Variable weak leaker values during read operations

Applying chip select for memory device identification and power management control

DDR memory bus with a reduced data strobe signal preamble timespan

Lower-power scrambling with improved signal integrity

Interference testing

Techniques for command bus training to a memory device

Techniques for command bus training to a memory device

On-die system electrostatic discharge protection

Disabling a command associated with a memory device

Disabling a command associated with a memory device

Suppressing power supply noise using data scrambling in double data rate memory systems

Applying chip select for memory device identification and power management control

I/O driver transmit swing control

DDR memory bus with a reduced data strobe signal preamble timespan

MOZAK CHRISTOPHER P

Memory subsystem command bus stress testing

Method and system for evaluating effects of signal phase difference on a memory system

Method, apparatus, and system for protecting supply nodes from electrostatic discharge

SCHOENBORN THEODORE Z

Active training of memory command timing

Memory subsystem I/O performance based on in-system empirical testing

COX CHRISTOPHER E

Mirroring memory commands to memory devices

Mechanism for facilitating dynamic multi-mode memory packages in memory systems

SONY GROUP CORP

Memory command that specifies one of multiple possible write data values where the write data is not transported over a memory data bus

Memory command that specifies one of multiple possible write data values where the write data is not transported over a memory data bus

BAINS KULJIT S

Row hammer refresh command

GREENFIELD ZVIKA

Row hammer condition monitoring

SPRY BRYAN L

Robust memory link testing using memory controller

MOSALIKANTI PRAVEEN

Methods and apparatuses for delay-locked loops and phase-locked loops