Inventor

CHEN DIAN-HAU

TW137 patents

⚠️ This page may combine multiple inventors who share the name “CHEN DIAN-HAU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN DIAN-HAU

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor device and manufacturing method thereof

Multi-layer passivation structure and method

Metal-insulator-metal structure

Chip structure and method for forming the same

Non-hierarchical metal layers for integrated circuits

Semiconductor structure having an air-gap region and a method of manufacturing the same

Metal-insulator-metal structure

Semiconductor arrangement and method of making

Semiconductor packages and method of manufacturing the same

Metal-Insulator-Metal structure

Metal-insulator-metal (MIM) capacitor structure

MRAM structure for balanced loading

Through vias of semiconductor structure and method of forming thereof

Prevention of metal pad corrosion due to exposure to halogen

Multilayer capacitor electrode

Metal-insulator-metal structure and methods of fabrication thereof

Metal-insulator-metal (MIM) capacitor structure and method for forming the same

Metal-insulator-metal structure and methods of fabrication thereof

Metal-insulator-metal (MIM) capacitor structure and method for forming the same

Metal-insulator-metal structure

Semiconductor device including a high density MIM capacitor and method

Semiconductor structure with polyimide packaging and manufacturing method

Low-stress passivation layer

Shielding structures

Metal plate corner structure on metal insulator metal

Semiconductor device comprising air gaps having different configurations

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Redistribution layers and methods of fabricating the same in semiconductor devices

Multilayer capacitor electrode

TAIWAN SEMICONDUCTOR MFG

Semiconductor structure having an air-gap region and a method of manufacturing the same

Methods of patterning small via pitch dimensions

Passivation and planarization process for flip chip packages

Inter-metal dielectric film composition for dual damascene process

RPO process for selective CoSix formation

CoSix process to improve junction leakage

Damascene method employing multi-layer etch stop layer

Photoresist scum free process for via first dual damascene process

Method of making a semiconductor device including barrier layers for copper interconnect

In-situ photoresist removal by an attachable chamber with light source

IMD film composition for dual damascene process

Chemical mechanical polish (CMP) planarizing method employing topographic mark preservation

LU LEE-CHUNG

Non-hierarchical metal layers for integrated circuits

Mask-shift-aware RC extraction for double patterning design

LIN CHUNG-YI

Methods of patterning small via pitch dimensions

HUANG CHENG-LIN

Partial air gap formation for providing interconnect isolation in integrated circuits

SU SHU-HUI

Semiconductor structure having an air-gap region and a method of manufacturing the same

LIU NAI-WEI

Barrier layers for copper interconnect