Inventor

CONFALONIERI EMANUELE

IT91 patents

⚠️ This page may combine multiple inventors who share the name “CONFALONIERI EMANUELE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CONFALONIERI EMANUELE

MICRON TECHNOLOGY INC

Multi-partitioning of memories

Temperature-based memory operations

Memory controller for managing data and error information

Data state synchronization

Multi-partitioning of memories

Controller for managing multiple types of memory

Read data path

Latency-based storage in a hybrid memory system

Multi-partitioning of memories

Latency-based storage in a hybrid memory system

Latency-based storage in a hybrid memory system

Data relocation in hybrid memory

Memory operations on data

Memory management

Unloaded cache bypass

Apparatus for redundant array of independent disks

Controllers and methods for accessing memory devices via multiple modes

Memory operations on data

Memory management

Data state synchronization

Memory operations on data

Memory management

Data state synchronization

Data state synchronization involving memory cells having an inverted data state written thereto

Multi-channel memory and power supply-driven channel selection

Apparatus, electronic devices and methods associated with an operative transition from a first interface to a second interface

Read data path

Controller cache architeture

Memory controller architecture

CONFALONIERI EMANUELE

Dynamic range unlock or lock memory device and method to operate the same

Memory with sub-blocks

Non-volatile memory with extended operating temperature range

Multi-channel memory and power supply-driven channel selection

Control and operation of non-volatile memory

PCM memories for storage bus interfaces

Temperature alert and low rate refresh for a non-volatile memory

Multi-channel memory and power supply-driven channel selection

Configurable partitions for non-volatile memory

Memory architecture

ST MICROELECTRONICS SRL

Decoding structure for a memory device with a control code

Non-volatile memory with a charge pump with regulated voltage

Circuit for biasing an input node of a sense amplifier with a pre-charge stage

Memory device with a ramp-like voltage biasing structure based on a current generator

Memory device

Sense amplifier structure for multilevel non-volatile memory devices and corresponding reading method

Output buffer for a nonvolatile memory with output signal switching noise reduction, and nonvolatile memory comprising the same

CARACCIO DANILO

Multi-partitioning feature on e-MMC

Multi-partitioning of memories

ALBINI GIULIO

Apparatus, electronic devices and methods associated with an operative transition from a first interface to a second interface

Multi-interface memory with access control