Inventor

ANG BOON JIN

MY36 patents

⚠️ This page may combine multiple inventors who share the name “ANG BOON JIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ANG BOON JIN

ALTERA CORP

Configuring a programmable logic device

Method for transferring data across different clock domains with selectable delay

Mask-programmable logic device with building block architecture

Clock divider using positive and negative edge triggered state machines

Data encoding scheme to reduce sense current

Techniques for combining volatile and non-volatile programmable logic on an integrated circuit

Isolation testing scheme for multi-die packages

LVDS output buffer pre-emphasis methods and apparatus

Techniques for performing built-in self-test of receiver channel having a serializer

Programmable logic configuration device with configuration memory accessible to a second device

Programmable soft macro memory using gate array base cells

Signal propagation circuitry for use on integrated circuits

Circuitry for facilitating performance of multiply-accumulate operations in programmable logic devices

Techniques for optimizing design of a hard intellectual property block for data transmission

High speed IO buffer

Techniques for reducing clock skew in clock routing networks

Techniques for debugging hard intellectual property blocks

Integrated circuit system with dynamic decoupling and method of manufacture thereof

Techniques for implementing hardwired decoders in differential input circuits

Techniques for optimizing design of a hard intellectual property block for data transmission

Dynamic real-time delay characterization and configuration

Delay circuit with delay cells in different orientations

Integrated circuit with dynamically-adjustable buffer space for serial interface

Programmable control of mask-programmable integrated circuit devices

TAN JUN PIN

Memory error detection circuitry

Data encoding scheme to reduce sense current

TAN ZUN YANG

Integrated circuit with dynamically-adjustable buffer space for serial interface

Configurable memory block

LIM TEIK WAH

Frequency control clock tuning circuitry

Frequency control clock tuning circuitry

CH NG CHIN GHEE

Memory circuitry with dynamic power control

FOO KOK YOONG

Multiplier with built-in accumulator

SOO SZE HUEY

Predicting routability of integrated circuits

SIA KET CHIEW

Integrated circuit with configurable I/O transistor arrangement

ANG BOON JIN

Method of designing integrated circuits including providing an option to select a mask layer set

MARURI VICTOR R

Method and apparatus for determining clock uncertainties