Inventor
YANG TE-SHENG
TW7 patents
Patents
7 patentsUS6204562B1Mar 20, 2001
Wafer-level chip scale package
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US6043109AMar 28, 2000
Method of fabricating wafer-level package
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US6291881B1Sep 18, 2001
Dual silicon chip package
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US6399421B2Jun 4, 2002
Dual-dies packaging structure and packaging method
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US6313527B1Nov 6, 2001
Dual-dies packaging structure and packaging method
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US6545350B2Apr 8, 2003
Integrated circuit packages and the method for the same
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US6846697B2Jan 25, 2005
Integrated circuit packages and the method for making the same
UNITED MICROELECTRONICS CORP0 citations51