Inventor

KASAI NAOKI

JP32 patents

⚠️ This page may combine multiple inventors who share the name “KASAI NAOKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KASAI NAOKI

NEC CORP

Isolation of insulated-gate field-effect transistors

Method for manufacturing a semiconductor device having contact plug made of Si/SiGe/Si

Embedded LSI having a FeRAM section and a logic circuit section

Method of forming a MOS transistor having gate insulators of different thicknesses

Method of forming MOS transistors having gate insulators of different thicknesses

Semiconductor memory device with memory cells having same characteristics and manufacturing method for the same

Embedded LSI having a FeRAM section and a logic circuit section

Semiconductor device and method for manufacturing same

MOS semiconductor device and method of manufacturing the same

Semiconductor device having contact plug and method for manufacturing the same

Semiconductor device capable of easily filling contact conductor plug in contact hole

Semiconductor device and fabrication process thereof

Small-sized multi-valued semiconductor memory device with coupled capacitors between divided bit lines

Semiconductor device having a self-aligned type contact hole

Semiconductor device with reduced number of intermediate level interconnection pattern and method of forming the same

Test device for insulated-gate field effect transistor and testing circuit and testing method using the same

Method for manufacturing contact structure capable of avoiding short-circuit

Method for manufacturing contact structure capable of avoiding short-circuit

Semiconductor device and fabrication method thereof

MOS semiconductor device and method of manufacturing the same

Semiconductor device with marginless contact hole

Semiconductor memory device with improved step protection and manufacturing method thereof

DRAM having a stacked capacitor and a method for fabricating the same

Characteristic-evaluating storage capacitors

MRAM and data read/write method for MRAM

Method of manufacturing semiconductor device in which hot carrier resistance can be improved and silicide layer can be formed with high reliability

Integrated circuit pattern lithography method capable of reducing the number of shots in partial batch exposure

Method of making a self-aligning type contact hole for a semiconductor device

Process for fabricating semiconductor device having semiconductor layers epitaxially grown from active areas without short-circuit on field insulating layer

Semiconductor memory device having memory cells similarly layouted and peripheral circuits symmetrically layouted in memory cell arrays

NEC ELECTRONICS CORP

Semiconductor device comprising high density integrated circuit having a large number of insulated gate field effect transistors

TOKYO SEIMITSU CO LTD

Wafer test system, probe card replacing method, and prober