Inventor
BARNAK JOHN P
US14 patents
Patents
14 patentsUS7022559B2Apr 4, 2006
MOSFET gate electrodes having performance tuned work functions and methods of making same
INTEL CORP216 citations99
US6858483B2Feb 22, 2005
Integrating n-type and p-type metal gate transistors
INTEL CORP81 citations98
US6696327B1Feb 24, 2004
Method for making a semiconductor device having a high-k gate dielectric
INTEL CORP85 citations98
US7316949B2Jan 8, 2008
Integrating n-type and p-type metal gate transistors
INTEL CORP50 citations96
US6972225B2Dec 6, 2005
integrating n-type and P-type metal gate transistors
INTEL CORP54 citations96
US6953719B2Oct 11, 2005
Integrating n-type and p-type metal gate transistors
INTEL CORP62 citations96
US6709911B1Mar 23, 2004
Method for making a semiconductor device having a high-k gate dielectric
INTEL CORP64 citations96
US6939815B2Sep 6, 2005
Method for making a semiconductor device having a high-k gate dielectric
INTEL CORP20 citations93
US6897134B2May 24, 2005
Method for making a semiconductor device having a high-k gate dielectric
INTEL CORP17 citations92
US6867102B2Mar 15, 2005
Method for making a semiconductor device having a high-k gate dielectric
INTEL CORP16 citations92
US6806146B1Oct 19, 2004
Method for making a semiconductor device having a high-k gate dielectric
INTEL CORP21 citations92
US7064446B2Jun 20, 2006
Under bump metallization layer to enable use of high tin content solder bumps
INTEL CORP29 citations87
US7567379B2Jul 28, 2009
Technique to prevent tin contamination of mirrors and electrodes in an EUV lithography system
INTEL CORP0 citations51
US7087521B2Aug 8, 2006
Forming an intermediate layer in interconnect joints and structures formed thereby
INTEL CORP0 citations51