Inventor

SCHRECK JOHN F

US76 patents

⚠️ This page may combine multiple inventors who share the name “SCHRECK JOHN F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHRECK JOHN F

TEXAS INSTRUMENTS INC

Method and circuitry for refreshing a flash electrically erasable, programmable read only memory

Segmented, multiple-decoder memory array and method for programming a memory array

Method and circuitry for programming floating-gate memory cell using a single low-voltage supply

EEPROM array with narrow margin of voltage thresholds after erase

Method and apparatus for EEPROM negative voltage wordline decoding

Method and apparatus for verifying the state of a plurality of electrically programmable memory cells

Offset floating gate EPROM memory cell

Threshold/voltage detection circuit

Bitline segmentation in logic arrays

Memory with I/O mappable redundant columns

Integrated circuit fuse-link tester and test method

Decoder driver circuit for programming high-capacitance lines

Nonvolatile memory array wordline driver circuit with voltage translator circuit

Switch for selectively coupling a power supply to a power bus

Nonvolatile memory device having program and/or erase voltage clamp

Common-line connection for integrated memory array

Voltage level detecting circuit

Method and apparatus for reading and programming electrically programmable memory cells

Skewed reference to improve ones and zeros in EPROM arrays

Output-buffer noise-control circuit

Array discharge for biased array

Staggered contacts in arrays of programmable memory cells

Extra row for testing programmability and speed of ROMS

Programming current controller

Equalized biased array for PROMS and EPROMS

Reference circuit for integrated memory arrays having virtual ground connections

Eprom pinout option

MICRON TECHNOLOGY INC

Apparatus and methods for regulated voltage

Asynchronous interface circuit and method for a pseudo-static memory device

Methods and apparatus for reducing decoder area

Sensing techniques using charge transfer device

Memory system and method using ECC with flag bit to identify modified data

Memory system and method using ECC with flag bit to identify modified data

Signal delivery in stacked device

Memory array error correction apparatus, systems, and methods

Asynchronous interface circuit and method for a pseudo-static memory device

Data storage based on data polarity

Tuning voltages in a read circuit

Apparatuses including a memory array with separate global read and write lines and/or sense amplifier region column select line and related methods

Data storage based on data polarity

Write techniques for a memory device with a charge transfer device

Data storage based on data polarity

Sensing techniques using a charge transfer device

Write techniques for a memory device with a charge transfer device

Sensing techniques using a charge transfer device

Memory device with a charge transfer device

KEETH BRENT

Signal delivery in stacked device

Signal delivery in stacked device

SCHRECK JOHN F

Bias circuitry for nonvolatile memory array

Memory array error correction apparatus, systems, and methods