Inventor

MCELROY DAVID J

US78 patents

⚠️ This page may combine multiple inventors who share the name “MCELROY DAVID J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MCELROY DAVID J

TEXAS INSTRUMENTS INC

Segmented, multiple-decoder memory array and method for programming a memory array

Dynamic memory array with segmented bit lines

Avalanche fuse element in programmable memory

High density floating gate electrically programmable ROM

Method of making a high density floating gate electrically programmable ROM

Method and circuitry for programming floating-gate memory cell using a single low-voltage supply

EEPROM array with narrow margin of voltage thresholds after erase

Fuse link for varying chip operating parameters

Block associative memory

Electrically erasable dual-injector floating gate programmable memory device

Memory system for microprocessor with multiplexed address/data bus

Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like

Memory system for microprocessor with multiplexed address/data bus

High density N-channel silicon gate read only memory

Digital processor system with direct access memory

High density N-channel silicon gate read only memory

Programming of an electrically-erasable, electrically-programmable, read-only memory array

Method of manufacturing an EEPROM with trench-isolated bitlines

Cross-point contact-free floating-gate memory array with silicided buried bitlines

EEPROM with trench-isolated bitlines

Cross-point contact-free floating-gate memory array with silicided buried bitlines

Dynamic ram cell with isolated trench capacitors

Single-ended sense amplifier for dynamic memory array

Process for making avalanche fuse element with isolated emitter

Avalanche fuse element as programmable device

Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like

Semiconductor integrated circuit with vertical implanted polycrystalline silicon resistor

EPROM and RAM cell layout with equal pitch for use in fault tolerant memory device or the like

High density floating gate EPROM programmable by charge storage

Electrically alterable floating gate semiconductor memory device with series enhancement transistor

Method of making an EEPROM cell with separate erasing and programming regions

Random access memory cell with ion implanted resistor element

Sense amplifier for CMOS semiconductor memory devices having symmetrically balanced layout

Contact programmable double level polysilicon MOS read only memory

Nonvolatile memory device having program and/or erase voltage clamp

Method of producing a self-aligned window at recessed intersection of insulating regions

Method of making an electrically-erasable, electrically-programmable read-only memory cell with self-aligned tunnel

Method of making an EEPROM with improved capacitive coupling between control gate and floating gate

Dynamic RAM cell with trench capacitor and trench transistor

Electrically-erasable, electrically-programmable read-only memory cell with self-aligned tunnel

MICRON TECHNOLOGY INC

Redundant imaging systems

Imaging system having redundant pixel groupings

Dynamic flash memory cells with ultrathin tunnel oxides

DRAM content addressable memory using part of the content as an address

Dynamic flash memory cells with ultra thin tunnel oxides

Reduced power DRAM device and method

Bias sensing in DRAM sense amplifiers

Bias sensing in DRAM sense amplifiers through voltage-coupling/decoupling device

Bias sensing in sense amplifiers through a voltage-coupling/decoupling device

Bias sensing in DRAM sense amplifiers through coupling and decoupling device