Inventor
PADALIA KETAN
CA22 patents
⚠️ This page may combine multiple inventors who share the name “PADALIA KETAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
16 patentsUS9569574B1Feb 14, 2017
Method and apparatus for performing fast incremental physical design optimization
ALTERA CORP35 citations93
US7558812B1Jul 7, 2009
Structures for LUT-based arithmetic in PLDs
ALTERA CORP25 citations92
US6871328B1Mar 22, 2005
Method for mapping logic design memory into physical memory device of a programmable logic device
ALTERA CORP39 citations92
US7681165B2Mar 16, 2010
Apparatus and methods for congestion estimation and optimization for computer-aided design software
ALTERA CORP21 citations90
US7370291B2May 6, 2008
Method for mapping logic design memory into physical memory devices of a programmable logic device
ALTERA CORP11 citations84
US7493585B1Feb 17, 2009
Methods of packing user logical RAM into dedicated RAM blocks and dual-use logic/RAM blocks
ALTERA CORP11 citations82
US7268584B1Sep 11, 2007
Adder circuitry for a programmable logic device
ALTERA CORP15 citations82
US9658830B1May 23, 2017
Structures for LUT-based arithmetic in PLDs
ALTERA CORP2 citations73
US11093672B2Aug 17, 2021
Method and apparatus for performing fast incremental physical design optimization
ALTERA CORP2 citations71
US10635772B1Apr 28, 2020
Method and apparatus for performing fast incremental physical design optimization
ALTERA CORP1 citations71
US8856713B1Oct 7, 2014
Method and apparatus for performing efficient incremental compilation
ALTERA CORP1 citations63
US7441208B1Oct 21, 2008
Methods for designing integrated circuits
ALTERA CORP3 citations62
US7415682B2Aug 19, 2008
Automatic adjustment of optimization effort in configuring programmable devices
ALTERA CORP3 citations62
US7707532B1Apr 27, 2010
Techniques for grouping circuit elements into logic blocks
ALTERA CORP4 citations61
US7275228B1Sep 25, 2007
Techniques for grouping circuit elements into logic blocks
ALTERA CORP3 citations61
US10073941B1Sep 11, 2018
Method and apparatus for performing efficient incremental compilation
ALTERA CORP0 citations52
PADALIA KETAN
4 patentsUS8281274B1Oct 2, 2012
Method and apparatus for performing efficient incremental compilation
PADALIA KETAN23 citations92
US8539418B1Sep 17, 2013
Method and apparatus for performing efficient incremental compilation
PADALIA KETAN10 citations83
US9594859B1Mar 14, 2017
Apparatus and associated methods for parallelizing clustering and placement
PADALIA KETAN8 citations82
US8788550B1Jul 22, 2014
Structures for LUT-based arithmetic in PLDs
PADALIA KETAN2 citations61