Inventor

BETZ VAUGHN

CA94 patents

⚠️ This page may combine multiple inventors who share the name “BETZ VAUGHN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BETZ VAUGHN

ALTERA CORP

Error correction for programmable logic integrated circuits

Apparatus and methods for adjusting performance of integrated circuits

Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability

Systems and methods for reducing static and total power consumption in a programmable logic device

Distributed random access memory in a programmable logic device

Method and apparatus for deriving signal activities for power analysis and optimization

Method and apparatus for performing path-level skew optimization and analysis for a logic design

Apparatus and methods for adjusting performance of integrated circuits

Apparatus and methods for power management in integrated circuits

Apparatus and methods for optimizing the performance of programmable logic devices

Bypass-able carry chain in a programmable logic device

Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool

Initializing a carry chain in a programmable logic device

Versatile logic element and logic array block

Routing architecture for a programmable logic device

Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage

Computer-aided-design tools for reducing power consumption in programmable logic devices

Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devices

Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage

Techniques for identifying functional blocks in a design that match a template and combining the functional blocks into fewer programmable circuit elements

Periphery clock distribution network for a programmable logic device

Distributed memory in field-programmable gate array integrated circuit devices

Method and apparatus for performing integrated global routing and buffer insertion

Distributed memory in field-programmable gate array integrated circuit devices

Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool for routing

Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability

Flexible I/O routing resources

Clock switch-over circuits and methods

Power-driven timing analysis and placement for programmable logic

Method and apparatus for performing incremental compilation

Variable delay circuitry

Routing architecture for a programmable logic device

Efficient delay elements

Systems and methods for reducing static and total power consumption in programmable logic device architectures

Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device

ALTERA TORONTO CO

Automatic generation of programmable logic device architectures

Heterogeneous interconnection architecture for programmable logic devices

Automatic generation of programmable logic device architectures

Heterogeneous interconnection architecture for programmable logic devices

LEWIS DAVID

Error correction for programmable logic integrated circuits

Apparatus and methods for adjusting performance of integrated circuits

Apparatus and methods for optimizing the performance of programmable logic devices using multiple supply voltage

FUNG RYAN

Method and apparatus for protecting, optimizing, and reporting synchronizers

Method and apparatus for performing path-level skew optimization and analysis for a logic design

ROSE JONATHAN

Complementary architecture for field-programmable gate arrays

BETZ VAUGHN

Method and apparatus for performing parallel routing using a multi-threaded routing procedure

PADALIA KETAN

Apparatus and associated methods for parallelizing clustering and placement

BORER TERRY

Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices

NETO DAVID

Method and apparatus for deriving signal activities for power analysis and optimization

MENDEL DAVID

Systems and methods for reducing static and total power consumption