Inventor

BALDI LIVIO

IT37 patents

⚠️ This page may combine multiple inventors who share the name “BALDI LIVIO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BALDI LIVIO

SGS THOMSON MICROELECTRONICS

Memory device having error detection and correction function, and methods for reading, writing and erasing the memory device

Method and device for uniforming luminosity and reducing phosphor degradation of a field emission flat display

Method of fabricating flat fed screens, and flat screen obtained thereby

Field emission display with diode-limited cathode current

Method for manufacturing MOS/CMOS monolithic integrated circuits including silicide and polysilicon patterning

High voltage capacitor

Process of fabricating tunnel-oxide nonvolatile memory devices

Process for realizing P-channel MOS transistors having a low threshold voltage in semiconductor integrated circuits for analog applications

Process for realizing P-channel MOS transistors having a low threshold voltage in semiconductor integrated circuits for analog applications

Method for making direct contacts in high density MOS/CMOS processes

Method of fabricating flat FED screens

Process for fabricating a microtip cathode assembly for a field emission display panel

Method of forming high-stability metallic contacts in an integrated circuit with one or more metallized layers

High-voltage N-channel MOS transistor and associated manufacturing process

ST MICROELECTRONICS SRL

Currency note comprising an integrated circuit

Method for formation of contact plugs utilizing etchback

NOR-type ROM with LDD cells and process of fabrication

Method of making NOR-type ROM with LDD cells

Method of manufacturing an integrated semiconductor device having a nonvolatile floating gate memory, and related integrated device

Method and device for supplying negative programming voltages to non-volatile memory cells in a non-volatile memory device

Method and device for supplying negative programming voltages to non-volatile memory cells in a non-volatile memory device

Method for manufacturing non-volatile memory cells on a semiconductor substrate

Method and device for supplying negative programming voltages to non-volatile memory cells in a non-volatile memory device

Matrix of memory cells fabricated by means of a self-aligned source process, comprising ROM memory cells, and related manufacturing process

Method for manufacturing non-volatile memory cells on a semiconductor substrate

Method of manufacturing an integrated semiconductor device having a nonvolatile floating gate memory, and related integrated device

SGS MICROELETTRONICA SPA

Nonvolatile, semiconductor memory device

Fabricating a CMOS transistor having low threshold voltages using self-aligned silicide polysilicon gates and silicide interconnect regions

Reduced-beak planox process for the formation of integrated electronic components

Method for making twin tub CMOS devices

MICRON TECHNOLOGY INC

Memory devices comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls and methods of forming a memory device comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls

Memory devices comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls and methods of forming a memory device comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls

Memory devices comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls and methods of forming a memory device comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls

Memory devices comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls and methods of forming a memory device comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls

ATES COMPONENTI ELETTRON

Metallization process of a wafer back

BRAZZELLI DANIELA

Method for manufacturing differential isolation structures in a semiconductor electronic device and corresponding structure

STMICROELETRONICS S R L

P-channel memory cell and method for forming the same