Inventor
DANGELO CARLOS
US36 patents
⚠️ This page may combine multiple inventors who share the name “DANGELO CARLOS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
28 patentsUS6470482B1Oct 22, 2002
Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation
LSI LOGIC CORP253 citations99
US5946487AAug 31, 1999
Object-oriented multi-media architecture
LSI LOGIC CORP352 citations99
US5933356AAug 3, 1999
Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models
LSI LOGIC CORP263 citations99
US5572437ANov 5, 1996
Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models
LSI LOGIC CORP149 citations99
US5544067AAug 6, 1996
Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation
LSI LOGIC CORP355 citations99
US5493508AFeb 20, 1996
Specification and design of complex digital systems
LSI LOGIC CORP151 citations99
US6324678B1Nov 27, 2001
Method and system for creating and validating low level description of electronic design
LSI LOGIC CORP264 citations98
US5910897AJun 8, 1999
Specification and design of complex digital systems
LSI LOGIC CORP107 citations98
US5838163ANov 17, 1998
Testing and exercising individual, unsingulated dies on a wafer
LSI LOGIC CORP137 citations98
US5801958ASep 1, 1998
Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information
LSI LOGIC CORP471 citations98
US5555201ASep 10, 1996
Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information
LSI LOGIC CORP356 citations98
US5553002ASep 3, 1996
Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, using milestone matrix incorporated into user-interface
LSI LOGIC CORP139 citations98
US5541849AJul 30, 1996
Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of timing parameters
LSI LOGIC CORP250 citations98
US5442282AAug 15, 1995
Testing and exercising individual, unsingulated dies on a wafer
LSI LOGIC CORP150 citations98
US5389556AFeb 14, 1995
Individually powering-up unsingulated dies on a wafer
LSI LOGIC CORP148 citations98
US6216252B1Apr 10, 2001
Method and system for creating, validating, and scaling structural description of electronic device
LSI LOGIC CORP337 citations97
US5870308AFeb 9, 1999
Method and system for creating and validating low-level description of electronic design
LSI LOGIC CORP212 citations97
US5648661AJul 15, 1997
Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies
LSI LOGIC CORP134 citations97
US5544066AAug 6, 1996
Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of low-level design constraints
LSI LOGIC CORP107 citations97
US5598344AJan 28, 1997
Method and system for creating, validating, and scaling structural description of electronic device
LSI LOGIC CORP120 citations96
US5557531ASep 17, 1996
Method and system for creating and validating low level structural description of electronic design from higher level, behavior-oriented description, including estimating power dissipation of physical implementation
LSI LOGIC CORP81 citations96
US5539325AJul 23, 1996
Testing and exercising individual, unsingulated dies on a wafer
LSI LOGIC CORP100 citations96
US5222030AJun 22, 1993
Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof
LSI LOGIC CORP130 citations96
US5572436ANov 5, 1996
Method and system for creating and validating low level description of electronic design
LSI LOGIC CORP77 citations94
US5526277AJun 11, 1996
ECAD system for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic descriptions thereof
LSI LOGIC CORP44 citations94
US5898677AApr 27, 1999
Integrated circuit device having a switched routing network
LSI LOGIC CORP22 citations92
US5615126AMar 25, 1997
High-speed internal interconnection technique for integrated circuits that reduces the number of signal lines through multiplexing
LSI LOGIC CORP45 citations92
US5880971AMar 9, 1999
Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from semantic specifications and descriptions thereof
LSI LOGIC CORP53 citations91
NANOCONDUCTION INC
4 patentsUS7109581B2Sep 19, 2006
System and method using self-assembled nano structures in the design and fabrication of an integrated circuit micro-cooler
NANOCONDUCTION INC111 citations98
US7656027B2Feb 2, 2010
In-chip structures and methods for removing heat from integrated circuits
NANOCONDUCTION INC47 citations92
US7732918B2Jun 8, 2010
Vapor chamber heat sink having a carbon nanotube fluid interface
NANOCONDUCTION INC29 citations86
US7538422B2May 26, 2009
Integrated circuit micro-cooler having multi-layers of tubes of a CNT array
NANOCONDUCTION INC37 citations86