Inventor

HALL RONALD P

US33 patents

⚠️ This page may combine multiple inventors who share the name “HALL RONALD P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HALL RONALD P

APPLE INC

Accessing memories in coherent and non-coherent domains in a computing system

Immediate branch recode that handles aliasing

Cache for patterns of instructions with multiple forward control transfers

Instruction loop buffer with tiered power savings

Prediction confirmation for cache subsystem

Fetch predition circuit for reducing power consumption in a processor

Cache flush method and apparatus

Reducing power consumption in a processor

Method to ensure forward progress of a processor in the presence of persistent external cache/TLB maintenance requests

Mechanism for reducing cache power consumption using cache way prediction

Virtual channel support using write table

Prediction confirmation for cache subsystem

Prediction confirmation for cache subsystem

Trace cache with filter for internal control transfer inclusion

Using a next fetch predictor circuit with short branches and return fetch groups

Trace cache techniques based on biased control transfer instructions

IBM

Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline

Handling data cache misses out-of-order for asynchronous pipelines

Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock condition

Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines

Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline

Selectively engaging optional data reduction mechanisms for capturing trace data

Pseudo-LRU virtual counter for a locking cache

Scaleable status tracking of multiple assist hardware threads

Method for data set replacement in 4-way or greater locking cache

Scalable link stack control method with full support for speculative operations

HALL RONALD P

Hardware assist thread for increasing code parallelism

Hardware assist thread for dynamic performance profiling

Hardware assist thread for increasing code parallelism

FRAZIER GILES ROGER

Obtaining and releasing hardware threads without hypervisor involvement

Obtaining and releasing hardware threads without hypervisor involvement

ABERNATHY CHRISTOPHER M

Issue unit for placing a processor into a gradual slow mode of operation

ARNDT RICHARD LOUIS

Scaleable status tracking of multiple assist hardware threads