Inventor
SHIPPY DAVID
US26 patents
⚠️ This page may combine multiple inventors who share the name “SHIPPY DAVID”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
21 patentsUS6820143B2Nov 16, 2004
On-chip data transfer in multi-processor system
IBM58 citations96
US5822755AOct 13, 1998
Dual usage memory selectively behaving as a victim cache for L1 cache or as a tag array for L2 cache
IBM59 citations96
US7401242B2Jul 15, 2008
Dynamic power management in a processor design
IBM22 citations92
US7350056B2Mar 25, 2008
Method and apparatus for issuing instructions from an issue queue in an information handling system
IBM32 citations92
US7103748B2Sep 5, 2006
Memory management for real-time applications
IBM21 citations92
US6981072B2Dec 27, 2005
Memory management in multiprocessor system
IBM34 citations92
US7596682B2Sep 29, 2009
Architected register file system utilizes status and control registers to control read/write operations between threads
IBM12 citations84
US7681056B2Mar 16, 2010
Dynamic power management in a processor design
IBM10 citations83
US7490224B2Feb 10, 2009
Time-of-life counter design for handling instruction flushes from a queue
IBM13 citations83
US7313673B2Dec 25, 2007
Fine grained multi-thread dispatch block mechanism
IBM18 citations83
US7114035B2Sep 26, 2006
Software-controlled cache set management with software-generated class identifiers
IBM8 citations74
US7900024B2Mar 1, 2011
Handling data cache misses out-of-order for asynchronous pipelines
IBM6 citations73
US7461239B2Dec 2, 2008
Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines
IBM7 citations73
US7913070B2Mar 22, 2011
Time-of-life counter for handling instruction flushes from a queue
IBM4 citations62
US7769985B2Aug 3, 2010
Load address dependency mechanism system and method in a high frequency, low power processor system
IBM2 citations62
US7370176B2May 6, 2008
System and method for high frequency stall design
IBM2 citations62
US7328330B2Feb 5, 2008
Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processor
IBM3 citations62
US7953960B2May 31, 2011
Method and apparatus for delaying a load miss flush until issuing the dependent instruction
IBM1 citations52
US7831808B2Nov 9, 2010
Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor
IBM0 citations52
US7363468B2Apr 22, 2008
Load address dependency mechanism system and method in a high frequency, low power processor system
IBM1 citations48
US7120748B2Oct 10, 2006
Software-controlled cache set management
IBM0 citations39
TEXAS INSTRUMENTS INC
2 patentsUS6061780AMay 9, 2000
Execution unit chaining for single cycle extract instruction having one serial shift left and one serial shift right execution units
TEXAS INSTRUMENTS INC71 citations96
US6003125ADec 14, 1999
High performance adder for multiple parallel add operations
TEXAS INSTRUMENTS INC10 citations74