Inventor

TEHRANI SAIED N

US71 patents

⚠️ This page may combine multiple inventors who share the name “TEHRANI SAIED N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TEHRANI SAIED N

MOTOROLA INC

Magnetic random access memory and fabricating method thereof

Low switching field magnetoresistive tunneling junction for high density arrays

Method of fabricating 3D multilayer semiconductor circuits

Magnetic random access memory and fabricating method thereof

Stray magnetic shielding for a non-volatile MRAM

Method of fabricating GMR devices

Multi-layer magnetic tunneling junction memory cells

Memory cell structure in a magnetic random access memory and a method for fabricating thereof

Magnetic element with dual magnetic states and fabrication method thereof

Method of fabricating flux concentrating layer for use with magnetoresistive random access memories

Method of fabricating a magnetic random access memory

Low switching field magnetic tunneling junction for high density arrays

Magnetic random access memory having stacked memory cells and fabrication method therefor

MRAM cell requiring low switching field

Multi-layer magnetic random access memory and method for fabricating thereof

Magnetic device having multi-layer with insulating and conductive layers

Method of selecting a memory cell in a magnetic random access memory device

Magnetic memory and method therefor

Multi-layer magnet tunneling junction memory cells

Low aspect ratio magnetoresistive tunneling junction

Nonvolatile programmable switch

Method of fabricating spaced apart submicron magnetic memory cells

Magnetic memory cell with increased GMR ratio

Multi-layer magnetic memory cells with improved switching characteristics

Mram with aligned magnetic vectors

MRAM with pinned ends

Ferromagnetic GMR material

Method of operating a random access memory device having a plurality of pairs of memory cells as the memory device

Logic circuit with negative differential resistance device

GMR device having a sense amplifier protected by a circuit for dissipating electric charges

Multi-layer magnetic memory cell with low switching current

Low threshold current laser

Heterojunction field effect transistor with monolayers in channel region

MRAM without isolation devices

Stable FET with shielding region in the substrate

Multi-piece cell and a MRAM array including the cell

Method for detecting information stored in a MRAM cell having two magnetic layers in different thicknesses

Complementary heterojunction device

Method of making high transconductance heterostructure field effect transistor

Superlattice field effect transistor with monolayer confinement

MRAM with high GMR ratio

Heterojunction interband tunnel diodes with improved P/V current ratios

Method of fabricating self-aligned FET structure having a high temperature stable T-shaped Schottky gate contact

Spin polarized apparatus

Current confinement via defect generator and hetero-interface interaction

Method of fabricating InAs/GaSb/AlSb material system SRAM

Resonant tunneling fet and methods of fabrication

Band-to-band resonant tunneling transistor

FREESCALE SEMICONDUCTOR INC

Method of fabricating a magnetic element with insulating veils

Method of fabricating a self-aligned via contact for a magnetic memory element