Inventor

WANG CHEN-JONG

TW113 patents

⚠️ This page may combine multiple inventors who share the name “WANG CHEN-JONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG CHEN-JONG

TAIWAN SEMICONDUCTOR MFG

Hybrid bonding mechanisms for semiconductor wafers

Method for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technology

Method of forming metal interconnect structures and metal via structures using photolithographic and electroplating or electro-less plating procedures

Multi-layer silicon nitride deposition method for forming low oxidation temperature thermally oxidized silicon nitride/silicon oxide (no) layer

Method for forming buried plug contacts on semiconductor integrated circuits

Method for fabricating a DRAM cell with a T shaped storage capacitor

Method to integrate high performance 1T ram in a CMOS process using asymmetric structure

Method for fabricating a dual-gate dielectric module for memory with embedded logic technology

Method of defining a buried stack capacitor structure for a one transistor RAM cell

Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure

Mixed mode process for embedded dram devices

Structure for a double wall tub shaped capacitor

Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure

Method of reducing nitride and oxide peeling after planarization using an anneal

Integration of SAC and salicide processes by combining hard mask and poly definition

Method for increasing DRAM capacitance via use of a roughened surface bottom capacitor plate

Method for fabricating a double wall tub shaped capacitor

Method for fabricating a DRAM cell with a Y shaped storage capacitor

Formation of self-aligned capacitor contact module in stacked cyclindrical dram cell

Method for fabricating a tub structured stacked capacitor for a DRAM cell having a central column

One step smooth cylinder surface formation process in stacked cylindrical DRAM products

Method of increasing the capacitance area in DRAM stacked capacitors using a simplified process

Microelectronic capacitor structure embedded within microelectronic isolation region

Method of forming a composite spacer to eliminate polysilicon stringers between elements in a pseudo SRAM cell

Method to increase DRAM capacitor via rough surface storage node plate

Method for making low-topography buried capacitor by a two stage etching process and device made

Process to fabricate stacked capacitor dram and low power thin film transistor sram devices on a single semiconductor chip

Process to fabricate stacked capacitor DRAM and low power thin film transistor SRAM devices on a single semiconductor chip

Method for forming buried plug contacts on semiconductor integrated circuits

High resistance polysilicon resistor for integrated circuits and method of fabrication thereof

Process for forming stacked contacts and metal contacts on static random access memory having thin film transistors

Process for forming stacked contacts and metal contacts on static random access memory having thin film transistors

Unified contact plug process for static random access memory (SRAM) having thin film transistors

Method of making a dram circuit with fin-shaped stacked capacitors

Approach for forming a buried stack capacitor structure featuring reduced polysilicon stringers

Decoupling MIM capacitor designs for interposers and methods of manufacture thereof

MIM capacitor structure and method of manufacture

Dual poly layer and method of manufacture

Common gate and salicide word line process for low cost embedded DRAM devices

TAIWAN SEMICONDUCTOR MFG CO LTD

Air trench in packages incorporating hybrid bonding

Hybrid bonding mechanisms for semiconductor wafers

Semiconductor image sensor

Implant damage free image sensor and method of the same

Voltage biased metal shielding and deep trench isolation for backside illuminated (BSI) image sensors

Air trench in packages incorporating hybrid bonding

Deep trench spacing isolation for complementary metal-oxide-semiconductor (CMOS) image sensors

Semiconductor arrangment with capacitor

TZENG KUO-CHYUAN

Method of manufacturing decoupling MIM capacitor designs for interposers

Method of fabricating metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers

CHEN KUO-JI

Metal-insulator-metal capacitor with current leakage protection