Inventor

SHIH JIAW-REN

TW63 patents

⚠️ This page may combine multiple inventors who share the name “SHIH JIAW-REN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHIH JIAW-REN

TAIWAN SEMICONDUCTOR MFG

STI process for improving isolation for deep sub-micron application

Combination erase waveform to reduce oxide trapping centers generation rate of flash EEPROM

Displacement current trigger SCR

Method for manufacturing short-channel, metal-gate CMOS devices with superior hot carrier performance

Clipped sine wave channel erase method to reduce oxide trapping charge generation rate of flash EEPROM

Electro-static discharge protection structure for semiconductor devices

Decoupling capacitor

Channel stop ion implantation method for CMOS integrated circuits

N-type structure for n-type pull-up and down I/O protection circuit

Modified source side inserted anti-type diffusion ESD protection device

Plasma damage protection cell using floating N/P/N and P/N/P structure

ESD protection circuit for different power supplies

Displacement current trigger SCR

Robust latchup-immune CMOS structure

Method of manufacture of CMOS device using additional implant regions to enhance ESD performance

ESD device protection structure and process with high tilt angle GE implant

Highly latchup-immune CMOS I/O structures

Method of manufacturing a highly latchup-immune CMOS I/O structure

Method of fabricating an ESD protection device

Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before or after a teos liner deposition

Uniform current distribution SCR device for high voltage ESD protection

Integration method for deep sub-micron dual gate transistor design

Undoped polysilicon gate process for NMOS ESD protection circuits

Gate process for NMOS ESD protection circuits

Asymmetrical layout structure for ESD protection

Diode for power protection

Clamping circuit for stacked NMOS ESD protection

Modified source side inserted anti-type diffusion ESD protection device

Method for fabricating a on-chip temperature controller by co-implant polysilicon resistor

Uniform current distribution SCR device for high voltage ESD protection

Plasma damage protection cell using floating N/P/N and P/N/P structure

Process to optimize performance and reliability of MOSFET devices

ESD protection structures on SOI substrates

Decoupling capacitor

ESD protection structure

CMOS device using additional implant regions to enhance ESD performance and device manufactured thereby

ESD protection circuit for different power supplies

Method of delta-channel in deep sub-micron process

ESD protect device structure

Process to improve temperature uniformity during RTA by deposition of in situ poly on the wafer backside

ESD protection scheme for outputs with resistor loading

Circuit system for protecting thin dielectric devices from ESD induced damages

Extended length metal line for improved ESD performance

Electrostatic discharge protective circuit for reducing an undesired channel turn-on

TAIWAN SEMICONDUCTOR MFG CO LTD

Fin field effect transistor (FinFET) device having position-dependent heat generation and method of making the same

Transistor and method of manufacturing the same

Method of making fin field effect transistor (FinFET) device

Fin field effect transistor (FinFET) device having position-dependent heat generation

Fin field effect transistor (FinFET) device having position-dependent heat generation

LIN BI-LING

Semiconductor device components and methods