Inventor

LIU KUO-CHIO

TW47 patents

⚠️ This page may combine multiple inventors who share the name “LIU KUO-CHIO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU KUO-CHIO

TAIWAN SEMICONDUCTOR MFG CO LTD

LTHC as charging barrier in InFO package formation

Method for forming semiconductor device structure with bumps

LTHC as charging barrier in InFO package formation

Package and package-on-package structure having elliptical conductive columns

Semiconductor die having edge with multiple gradients and method for forming the same

Chip package structure including ring-like structure and method for forming the same

Package on package structure

Method of manufacturing semiconductor structure

Method for forming package structure including intermetallic compound

Bump layout for coplanarity improvement

Semiconductor structure and fabricating method thereof

Dummy through vias for integrated circuit packages and methods of forming the same

Method of forming integrated circuit packages by bonding package component having first carrier to package substrate having second carrier

Forming bonding structures by using template layer as templates

Lthc as charging barrier in info package formation

Method for forming semiconductor die having edge with multiple gradients

Package and package-on-package structure having elliptical columns and ellipsoid joint terminals

LTHC as charging barrier in info package formation

Package and package-on-package structure having elliptical columns and ellipsoid joint terminals

Package and package-on-package structure having elliptical columns and ellipsoid joint terminals

Semiconductor die having edge with multiple gradients and method for forming the same

Chip package structure with ring-like structure

Package on package structure

Chip package structure with ring-like structure

Chip package structure with ring-like structure

Package on package structure

Method of manufacturing semiconductor structure

Package structure with a barrier layer

Method for forming package structure with a barrier layer

Multi-die package and methods of formation

Forming bonding structures by using template layer as templates

Method of manufacturing semiconductor structure

Semiconductor structure and manufacturing method thereof

Package structure with a barrier layer and method for forming the same

TAIWAN SEMICONDUCTOR MFG

Combined NMOS and SCR ESD protection device

Two step molding grinding for packaging applications

High voltage ESD protection device with very low snapback voltage by adding as a p+ diffusion and n-well to the NMOS drain

Uniform current distribution SCR device for high voltage ESD protection

High voltage transistor using P+ buried layer

Uniform current distribution SCR device for high voltage ESD protection

High voltage device embedded non-volatile memory cell and fabrication method

High voltage ESD protection device with very low snapback voltage

High voltage transistor using P+ buried layer

Twin current bipolar device with hi-lo base profile

Field ring to improve the breakdown voltage for a high voltage bipolar device

High voltage transistor using P+ buried layer

Twin current bipolar device with hi-lo base profile