Inventor

KIM HYEON-SEAG

US34 patents

⚠️ This page may combine multiple inventors who share the name “KIM HYEON-SEAG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIM HYEON-SEAG

ADVANCED MICRO DEVICES INC

Epitaxial silicon growth and usage of epitaxial gate insulator for low power, high performance devices

Fabrication of P-channel field effect transistor with minimized degradation of metal oxide gate

High density floating gate flash memory and fabrication processes therefor

MOS transistors with high-k dielectric gate insulator for reducing remote scattering

High density floating gate flash memory and fabrication processes therefor

Method and apparatus for predicting semiconductor device lifetime

Method and system for qualifying an ONO layer in a semiconductor device

Fabrication of gate of P-channel field effect transistor with added implantation before patterning of the gate

Determination of device failure characteristic

Flash memory cell with minimized floating gate to drain/source overlap for minimizing charge leakage

Hot carrier oxide qualification method

Process to improve the Vss line formation for high density flash memory and related structure associated therewith

High voltage oxidation method for highly reliable flash memory devices

Method for fabricating self-aligned gate of flash memory cell

Test structure for determining electromigration and interlayer dielectric failure

Semiconductor component and method of manufacture and monitoring

Method for determining a Weibull slope having a bias voltage variation adjustment

Method of detecting shallow trench isolation corner thinning by electrical stress

Method for increasing core gain in flash memory device using strained silicon

Space-saving test structures having improved capabilities

Maximum VCC calculation method for hot carrier qualification

Method for adjusting a Weibull slope for variations in temperature and bias voltage

MOSFET with SiGe source/drain regions and epitaxial gate dielectric

Method and system for determining an operating voltage using a source/drain to gate overlap induced scaling factor

Method and system for providing source/drain-gate spatial overlap engineering for low-power devices

Method and system for reducing thinning of field isolation structures in a flash memory device

Method and system for qualifying an ONO layer in a semiconductor device

Method of detecting shallow trench isolation corner thinning by electrical trapping

Structure and method for a two-bit memory cell

VANTIS CORP

Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench

Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress

Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress

Fabrication of oxide regions having multiple thicknesses using minimized number of thermal cycles

Gate insulator process for nanometer MOSFETS