Inventor

ALLMAN DERRYL D J

US74 patents

⚠️ This page may combine multiple inventors who share the name “ALLMAN DERRYL D J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ALLMAN DERRYL D J

LSI LOGIC CORP

Tunable dielectric constant oxide and method of manufacture

Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same

Integrated circuit device having a capacitor with the dielectric peripheral region being greater than the dielectric central region

Method and apparatus for detecting a polishing endpoint based upon heat conducted through a semiconductor wafer

Subsonic to supersonic and ultrasonic conditioning of a polishing pad in a chemical mechanical polishing apparatus

Interconnect-embedded metal-insulator-metal capacitor

Interconnect-integrated metal-insulator-metal capacitor and method of fabricating same

Capacitor with multiple-component dielectric and method of fabricating same

Method of forming a metal-insulator-metal capacitor in an interconnect cavity

Substrate planarization with a chemical mechanical polishing stop layer

Method and apparatus for detecting a planarized outer layer of a semiconductor wafer with a confocal optical system

On-chip multiple layer vertically transitioning optical waveguide and damascene method of fabricating the same

Integrated circuit device and method of making the same using chemical mechanical polishing to remove material in two layers following masking

Method and apparatus for detecting a polishing endpoint based upon infrared signals

Method and apparatus for detecting a planarized outer layer of a semiconductor wafer with a confocal optical system

Subsonic to supersonic and ultrasonic conditioning of a polishing pad in a chemical mechanical polishing apparatus

Apparatus and method of detecting a polishing endpoint layer of a semiconductor wafer which includes a metallic reporting substance

Process for removal of resist mask over low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and removal of residues from via etch and resist mask removal

Fabrication of metal-insulator-metal capacitive structures

Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same

Polishing composition for CMP operations

Method for tungsten nucleation from WF6 using titanium as a reducing agent

On-chip graded index of refraction optical waveguide and damascene method of fabricating the same

Capacitor with stoichiometrically adjusted dielectric and method of fabricating same

Bond pad design

Process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure

On-chip single layer horizontal deflecting waveguide and damascene method of fabricating the same

On-chip single layer horizontal deflecting waveguide and damascene method of fabricating the same

NCR CO

Global planarization using SOG and CMP

Silica-based anti-reflective planarizing layer

Coating solution for forming glassy layers

Spin-on glass composition

Method of making a shallow junction by using first and second SOG layers

Native oxide reduction for sealing nitride deposition

Method for forming a bipolar emitter using doped SOG

HYUNDAI ELECTRONICS AMERICA

Coating solution for forming glassy layers

Bonding of silicon wafers

Bonding of silicon wafers

Global planarization using SOG and CMP

Integrated circuit device comprising low dielectric constant material for reduced cross talk

Method for using low dielectric constant material in integrated circuit fabrication

Integrated circuit device with reduced cross talk

AT & T GLOBAL INF SOLUTION

Spin-on conductor process for integrated circuits

Electronic device with a spin-on glass dielectric layer

Electronic device with a spin-on glass dielectric layer

Method for using low dielectric constant material in integrated circuit fabrication

Method for manufacturing a monitor element

SYMBIOS LOGIC INC

Method for polishing a wafer

LSI LGOIC CORP

Apparatus and method of planarizing a semiconductor wafer that includes a first reflective substance and a second reflective substance

LSI CORP

Integrated circuit with inductor having horizontal magnetic flux lines