Inventor

CHANG KUANG-YEH

TW87 patents

⚠️ This page may combine multiple inventors who share the name “CHANG KUANG-YEH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG KUANG-YEH

UNITED MICROELECTRONICS CORP

ROM diode and a method of making the same

Method of fabricating one-time programmable read only memory

High density ROM and a method of making the same

Method of decoding a diode type read only memory

Method of manufacturing CMOS sensor

CMOS sensor

Flash memory

Methods of programming, erasing and reading a flash memory

High density ROM and a method of making the same

Method of fabricating dual damascene structure

Method of fabricating dual damascene structure

Method for eliminating bridging defect in via first dual damascene process

Method for preventing electrostatic discharge in a clean room

Method of manufacturing high voltage mixed-mode device

Method of fabricating mixed-mode semiconductor device having a capacitor and a gate

Method of forming mixed mode devices

Method for fabricating one time programmable read only memory

Read method for reading data from a high-density semiconductor read-only memory device

Method of decoding a diode type read only memory

ADVANCED MICRO DEVICES INC

Method for forming advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits

Reverse damascene via structures

Advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits

Nitrogenated trench liner for improved shallow trench isolation

Reverse CMOS method for dual isolation semiconductor device

SRAM cell having single layer polysilicon thin film transistors

Electro-static discharge protection device for CMOS integrated circuit inputs

Method of forming low resistance contact structures in vias arranged between two levels of interconnect lines

Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties

Integrated circuit having improved polysilicon resistor structures

Method of fabricating field effect transistors having lightly doped drain regions

Lightly doped drain profile optimization with high energy implants

Method of making simplified LDD and source/drain formation in advanced CMOS integrated circuits using implantation through well mask

Method of fabricating FET or CMOS transistors using MeV implantation

Method for forming an integrated circuit having improved polysilicon resistor structures

Semiconductor trench isolation with improved planarization methodology

Reduced bird&#39;s beak field oxidation process using nitrogen implanted into active region

Advanced isolation scheme for deep submicron technology

Reduced bird&#39;s beak field oxidation process using nitrogen implanted into active region

VLSI TECHNOLOGY INC

Method for making multi-level antifuse structure

Method of making flash memory cell

Method for making anti-fuse structures

Anti-fuse structures and methods for making same

Low voltage CMOS process and device with individually adjustable LDD spacers

Multi-level antifuse structure

Method for making cusp-free anti-fuse structures

MOTOROLA INC

Modified source/drain implants in a double-poly non-volatile memory process

CMOS process flow with small gate geometry LDO N-channel transistors

HUGHES AIRCRAFT CO

Double layer photoresist technique for side-wall profile control in plasma etching processes

VLSI TECHOLOGY INC

Double poly process with independently adjustable interpoly dielectric thickness

GETAC TECHNOLOGY CORP

Buckle

Reduced bird's beak field oxidation process using nitrogen implanted into active region

Reduced bird's beak field oxidation process using nitrogen implanted into active region