Inventor

VERMA PURAKH RAJ

SG139 patents

⚠️ This page may combine multiple inventors who share the name “VERMA PURAKH RAJ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VERMA PURAKH RAJ

CHARTERED SEMICONDUCTOR MFG

Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process

Method of reducing substrate coupling/noise for radio frequency CMOS (RFCMOS) components in semiconductor technology by backside trench and fill

Method to enhance inductor Q factor by forming air gaps below inductors

High gain lateral PNP and NPN bipolar transistor and process compatible with CMOS for making BiCMOS circuits

Method for making high gain lateral PNP and NPN bipolar transistor compatible with CMOS for making BICMOS circuits

Method for forming a thin-film, electrically blowable fuse with a reproducible blowing wattage

LDMOS using a combination of enhanced dielectric stress layer and dummy gates

Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process

Heterojunction bipolar transistor using reverse emitter window

Method of reducing substrate coupling for chip inductors by creation of dielectric islands by selective EPI deposition

Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth

Vertical polysilicon diode compatible with CMOS/BiCMOS integrated circuit processes

Method for forming vertical polysilicon diode compatible with CMOS/BICMOS formation

Method of making direct contact on gate by using dielectric stop layer

Method of integrating triple gate oxide thickness

Use of a selective hard mask for the integration of double diffused drain MOS devices in deep sub-micron fabrication technologies

UNITED MICROELECTRONICS CORP

Semiconductor device comprising a deep trench isolation structure and a trap rich isolation structure in a substrate and a method of making the same

Semiconductor structure with back gate and method of fabricating the same

Semiconductor structure with an air gap

Method of fabricating an air gap

Semiconductor device and method of fabricating the same

Semiconductor structure and manufacturing method thereof

Integrated circuit device and fabrication method thereof

Integrated circuit device

Semiconductor device

Semiconductor structure and manufacturing method thereof

Semiconductor structure and manufacturing method thereof

Semiconductor structure and method of wafer bonding

Seal ring structure

GLOBALFOUNDRIES SG PTE LTD

Integrated circuits with contacts through a buried oxide layer and methods of producing the same

Semiconductor devices including avalanche photodetector diodes integrated on waveguides and methods for fabricating the same

Creation of wide band gap material for integration to SOI thereof

Isolation scheme for high voltage device

Integrated circuit comprising on-chip resistors with plurality of first and second terminals coupled to the resistor body

Self-aligned high voltage LDMOS

Grounding of silicon-on-insulator structure

Integrated circuits with laterally diffused metal oxide semiconductor structures and methods for fabricating the same

Integrated circuits with laterally diffused metal oxide semiconductor structures and methods for fabricating the same

Semiconductor devices including photodetectors integrated on waveguides and methods for fabricating the same

Integrated circuits with laterally diffused metal oxide semiconductor structures

Methods for fabricating integrated circuits including substrate contacts

ZHANG GUOWEI

Stress enhanced high voltage device

High voltage device

High voltage device

MOS with recessed lightly-doped drain

High voltage device

VERMA PURAKH RAJ

Self-aligned body fully isolated device

Integration of trench MOS with low voltage integrated circuits

Integration of germanium photo detector in CMOS processing

Integration of high voltage trench transistor with low voltage CMOS transistor