Inventor

TANG STEPHEN H

US62 patents

⚠️ This page may combine multiple inventors who share the name “TANG STEPHEN H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TANG STEPHEN H

INTEL CORP

Floating-body memory cell write

Purge-based floating body memory

OTP antifuse cell and cell array

Method and apparatus to clamp SRAM supply voltage

Wide-range local bias generator for body bias grid

2-transistor floating-body dram

Method and apparatus to clamp SRAM supply voltage

Reducing power consumption in integrated circuits

Dual gate oxide one time programmable (OTP) antifuse cell

Apparatus and method for programming a memory array

1P1N 2T gain cell

Floating-body dynamic random access memory and method of fabrication in tri-gate technology

Memory with reduced sub-threshold leakage current in dynamic bit lines of read ports

Bias generator for body bias

Component reliability budgeting system

Method, apparatus and system of adjusting one or more performance-related parameters of a processor

Two transistor gain cell, method, and system

Crosspoint memory array utilizing one time programmable antifuse cells

Processor apparatus with body bias circuitry to delay thermal throttling

Apparatus and method for a one-phase write to a one-transistor memory cell array

Temperature and/or process independent current generation circuit

Non volatile data storage through dielectric breakdown

Floating-body dynamic random access memory and method of fabrication in tri-gate technology

Component reliability budgeting system

SRAM cell power reduction circuit

Overvoltage detection apparatus, method, and system

Floating-body dynamic random access memory with purge line

Floating-body dynamic random access memory with purge line

Bias generation circuit

SRAM device having forward body bias control

Memory cell without halo implant

Capacitor structure for a logic process

MICRON TECHNOLOGY INC

Memory array decoding and interconnects

Apparatuses, memories, and methods for address decoding and selecting an access line

Apparatuses, memories, and methods for address decoding and selecting an access line

Apparatuses, memories, and methods for address decoding and selecting an access line

Memory array decoding and interconnects

Apparatuses, memories, and methods for address decoding and selecting an access line

Memory array decoding and interconnects

Buried lines and related fabrication techniques

Cross-point memory array with access lines

Thin film transistors and related fabrication techniques

Memory array decoding and interconnects

Cross-point memory array and related fabrication techniques

Apparatuses, memories, and methods for address decoding and selecting an access line

Thin film transistors and related fabrication techniques

Cross-point memory array and related fabrication techniques

Buried lines and related fabrication techniques

OVONYX INC

Electrostatic discharge protection circuit including ovonic threshold switches

NARENDRA SIVA G

Component reliability budgeting system