Inventor
CORY WARREN E
US22 patents
⚠️ This page may combine multiple inventors who share the name “CORY WARREN E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XILINX INC
19 patentsUS6617877B1Sep 9, 2003
Variable data width operation in multi-gigabit transceivers on a programmable logic device
XILINX INC77 citations98
US7519747B1Apr 14, 2009
Variable latency buffer and method of operation
XILINX INC57 citations97
US7913104B1Mar 22, 2011
Method and apparatus for receive channel data alignment with minimized latency variation
XILINX INC36 citations92
US7623660B1Nov 24, 2009
Method and system for pipelined decryption
XILINX INC27 citations92
US7426678B1Sep 16, 2008
Error checking parity and syndrome of a block of data with relocated parity bits
XILINX INC21 citations92
US7295639B1Nov 13, 2007
Distributed adaptive channel bonding control for improved tolerance of inter-channel skew
XILINX INC33 citations92
US7187709B1Mar 6, 2007
High speed configurable transceiver architecture
XILINX INC27 citations92
US7099426B1Aug 29, 2006
Flexible channel bonding and clock correction operations on a multi-block data path
XILINX INC27 citations92
US6970013B1Nov 29, 2005
Variable data width converter
XILINX INC46 citations92
US10528513B1Jan 7, 2020
Circuit for and method of providing a programmable connector of an integrated circuit device
XILINX INC16 citations84
US10038450B1Jul 31, 2018
Circuits for and methods of transmitting data in an integrated circuit
XILINX INC12 citations84
US7382823B1Jun 3, 2008
Channel bonding control logic architecture
XILINX INC9 citations84
US7111220B1Sep 19, 2006
Network physical layer with embedded multi-standard CRC generator
XILINX INC16 citations84
US10623174B1Apr 14, 2020
Low latency data transfer technique for mesochronous divided clocks
XILINX INC9 citations82
US7895509B1Feb 22, 2011
Error checking parity and syndrome of a block of data with relocated parity bits
XILINX INC4 citations74
US7088767B1Aug 8, 2006
Method and apparatus for operating a transceiver in different data rates
XILINX INC10 citations74
US6960933B1Nov 1, 2005
Variable data width operation in multi-gigabit transceivers on a programmable logic device
XILINX INC6 citations74
US10033523B1Jul 24, 2018
Circuit for and method of measuring latency in an integrated circuit
XILINX INC6 citations72
US12248761B2Mar 11, 2025
Deterministic reset mechanism for asynchronous gearbox FIFOs for predictable latency
XILINX INC0 citations61
CORY WARREN E
3 patentsUS8245102B1Aug 14, 2012
Error checking parity and syndrome of a block of data with relocated parity bits
CORY WARREN E23 citations92
US8411703B1Apr 2, 2013
Method and apparatus for a reduced lane-lane skew, low-latency transmission system
CORY WARREN E23 citations91
US8301988B1Oct 30, 2012
Error checking parity and syndrome of a block of data with relocated parity bits
CORY WARREN E1 citations62