Inventor
HU CHUAN
US73 patents
⚠️ This page may combine multiple inventors who share the name “HU CHUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
29 patentsUS7420273B2Sep 2, 2008
Thinned die integrated circuit package
INTEL CORP63 citations98
US7319048B2Jan 15, 2008
Electronic assemblies having a low processing temperature
INTEL CORP17 citations93
US7012011B2Mar 14, 2006
Wafer-level diamond spreader
INTEL CORP23 citations93
US7009289B2Mar 7, 2006
Fluxless die-to-heat spreader bonding using thermal interface material
INTEL CORP39 citations93
US6833289B2Dec 21, 2004
Fluxless die-to-heat spreader bonding using thermal interface material
INTEL CORP27 citations93
US7888183B2Feb 15, 2011
Thinned die integrated circuit package
INTEL CORP17 citations92
US7882624B2Feb 8, 2011
Method of forming electronic package having fluid-conducting channel
INTEL CORP19 citations92
US7259965B2Aug 21, 2007
Integrated circuit coolant microchannel assembly with targeted channel configuration
INTEL CORP40 citations92
US7126822B2Oct 24, 2006
Electronic packages, assemblies, and systems with fluid cooling
INTEL CORP32 citations92
US7038316B2May 2, 2006
Bumpless die and heat spreader lid module bonded to bumped die carrier
INTEL CORP34 citations92
US7646093B2Jan 12, 2010
Thermal management of dies on a secondary side of a package
INTEL CORP28 citations90
US7095111B2Aug 22, 2006
Package with integrated wick layer and method for heat removal
INTEL CORP25 citations90
US10122089B2Nov 6, 2018
Magnetic nanocomposite materials and passive components formed therewith
INTEL CORP7 citations84
US9543197B2Jan 10, 2017
Package with dielectric or anisotropic conductive (ACF) buildup layer
INTEL CORP7 citations84
US7476568B2Jan 13, 2009
Wafer-level assembly of heat spreaders for dual IHS packages
INTEL CORP6 citations74
US10867961B2Dec 15, 2020
Single layer low cost wafer level packaging for SFF SiP
INTEL CORP4 citations73
US10381288B2Aug 13, 2019
Packaged semiconductor die and CTE-engineering die pair
INTEL CORP2 citations73
US10014277B2Jul 3, 2018
Single layer low cost wafer level packaging for SFF SiP
INTEL CORP2 citations73
US9942980B2Apr 10, 2018
Wavy interconnect for bendable and stretchable devices
INTEL CORP5 citations73
US9761514B2Sep 12, 2017
Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
INTEL CORP2 citations73
US9673131B2Jun 6, 2017
Integrated circuit package assemblies including a glass solder mask layer
INTEL CORP5 citations73
US9530747B2Dec 27, 2016
Solder in cavity interconnection structures
INTEL CORP3 citations72
US7091108B2Aug 15, 2006
Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices
INTEL CORP9 citations71
US7713839B2May 11, 2010
Diamond substrate formation for electronic assemblies
INTEL CORP6 citations63
US7626251B2Dec 1, 2009
Microelectronic die assembly having thermally conductive element at a backside thereof and method of making same
INTEL CORP2 citations63
US7279796B2Oct 9, 2007
Microelectronic die having a thermoelectric module
INTEL CORP2 citations63
US7560640B2Jul 14, 2009
Densely packed thermoelectric cooler
INTEL CORP4 citations61
US7531429B2May 12, 2009
Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices
INTEL CORP2 citations60
US9848490B2Dec 19, 2017
Solder in cavity interconnection technology
INTEL CORP0 citations52
HU CHUAN
8 patentsUS9281292B2Mar 8, 2016
Single layer low cost wafer level packaging for SFF SiP
HU CHUAN54 citations97
US9685390B2Jun 20, 2017
Microelectronic package having non-coplanar, encapsulated microelectronic devices and a bumpless build-up layer
HU CHUAN9 citations84
US9072187B2Jun 30, 2015
Off-plane conductive line interconnects in microelectronic devices
HU CHUAN9 citations84
US8424748B2Apr 23, 2013
Solder in cavity interconnection technology
HU CHUAN8 citations84
US9741645B2Aug 22, 2017
Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures and packages
HU CHUAN3 citations73
US8080870B2Dec 20, 2011
Die-warpage compensation structures for thinned-die devices, and methods of assembling same
HU CHUAN3 citations63
US9006890B2Apr 14, 2015
Solder in cavity interconnection structures
HU CHUAN2 citations62
US10096535B2Oct 9, 2018
Packaged semiconductor die and CTE-engineering die pair
HU CHUAN0 citations52
MICROSOFT TECHNOLOGY LICENSING LLC
3 patentsUS11874882B2Jan 16, 2024
Extracting key phrase candidates from documents and producing topical authority ranking
MICROSOFT TECHNOLOGY LICENSING LLC2 citations72
US11657223B2May 23, 2023
Keyphase extraction beyond language modeling
MICROSOFT TECHNOLOGY LICENSING LLC2 citations71
US11250214B2Feb 15, 2022
Keyphrase extraction beyond language modeling
MICROSOFT TECHNOLOGY LICENSING LLC0 citations60
LU DAOQIANG
2 patentsSHENZHEN XIUYUAN ELECTRONIC TECH CO LTD
2 patentsLYNXI TECH CO LTD
2 patentsMA QING
1 patentNAIR VIJAY K
1 patentOPPLE LIGHTING CO LTD
1 patentINST OF SEMICONDUCTORS GUANGDONG ACADEMY OF SCIENCES
1 patentShowing the top 50 of 73 patents by PatentIndex Score.