Inventor
VASEKIN VLADIMIR
GB28 patents
⚠️ This page may combine multiple inventors who share the name “VASEKIN VLADIMIR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ADVANCED RISC MACH LTD
27 patentsUS7707390B2Apr 27, 2010
Instruction issue control within a multi-threaded in-order superscalar processor
ADVANCED RISC MACH LTD29 citations92
US7178011B2Feb 13, 2007
Predication instruction within a data processing system
ADVANCED RISC MACH LTD44 citations92
US7529889B2May 5, 2009
Data processing apparatus and method for performing a cache lookup in an energy efficient manner
ADVANCED RISC MACH LTD9 citations84
US7802080B2Sep 21, 2010
Null exception handling
ADVANCED RISC MACH LTD17 citations83
US7447883B2Nov 4, 2008
Allocation of branch target cache resources in dependence upon program instructions within an instruction queue
ADVANCED RISC MACH LTD7 citations73
US11416252B2Aug 16, 2022
Program instruction fusion
ADVANCED RISC MACH LTD4 citations70
US9645824B2May 9, 2017
Branch target address cache using hashed fetch addresses
ADVANCED RISC MACH LTD2 citations70
US7447871B2Nov 4, 2008
Data access program instruction encoding
ADVANCED RISC MACH LTD3 citations62
US7386709B2Jun 10, 2008
Controlling execution of a block of program instructions within a computer processing system
ADVANCED RISC MACH LTD5 citations62
US7231507B2Jun 12, 2007
Data access program instruction encoding
ADVANCED RISC MACH LTD5 citations62
US11366668B1Jun 21, 2022
Method and apparatus for comparing predicated load value with masked load value
ADVANCED RISC MACH LTD0 citations61
US7489752B2Feb 10, 2009
Synchronisation of signals between asynchronous logic
ADVANCED RISC MACH LTD3 citations60
US7533241B2May 12, 2009
Variable size cache memory support within an integrated circuit
ADVANCED RISC MACH LTD2 citations58
US7877587B2Jan 25, 2011
Branch prediction within a multithreaded processor
ADVANCED RISC MACH LTD6 citations56
US8010774B2Aug 30, 2011
Breakpointing on register access events or I/O port access events
ADVANCED RISC MACH LTD2 citations53
US7111126B2Sep 19, 2006
Apparatus and method for loading data values
ADVANCED RISC MACH LTD6 citations53
US11194577B2Dec 7, 2021
Instruction issue according to in-order or out-of-order execution modes
ADVANCED RISC MACH LTD0 citations52
US12292834B2May 6, 2025
Cache prefetching
ADVANCED RISC MACH LTD0 citations50
US11947460B2Apr 2, 2024
Treating multiple cache lines as a merged cache line to store multiple blocks of data
ADVANCED RISC MACH LTD0 citations50
US11429393B2Aug 30, 2022
Apparatus and method for supporting out-of-order program execution of instructions
ADVANCED RISC MACH LTD0 citations50
US11409532B1Aug 9, 2022
Selecting instructions for a value predictor
ADVANCED RISC MACH LTD0 citations50
US11403105B2Aug 2, 2022
Detecting misprediction when an additional branch direction prediction determined using value prediction is considered more accurate than an initial branch direction prediction
ADVANCED RISC MACH LTD0 citations50
US10296349B2May 21, 2019
Allocating a register to an instruction using register index information
ADVANCED RISC MACH LTD0 citations46
US7360061B2Apr 15, 2008
Program instruction decompression and compression techniques
ADVANCED RISC MACH LTD0 citations41
US10719329B2Jul 21, 2020
Apparatus and method for using predicted result values
ADVANCED RISC MACH LTD0 citations39
US10620962B2Apr 14, 2020
Appratus and method for using predicted result values
ADVANCED RISC MACH LTD0 citations39
US7900019B2Mar 1, 2011
Data access target predictions in a data processing system
ADVANCED RISC MACH LTD0 citations35